From 7c2a0a6ad20412063e1f2723eb0ed38d5231c7da Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Jul 2020 11:28:14 -0600
Subject: [PATCH] streamline fabric verilog options

---
 openfpga/src/fpga_verilog/fabric_verilog_options.cpp |  3 ---
 openfpga/src/fpga_verilog/fabric_verilog_options.h   | 11 -----------
 2 files changed, 14 deletions(-)

diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
index ba843ef20..3bf851659 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
@@ -18,9 +18,6 @@ FabricVerilogOption::FabricVerilogOption() {
   include_timing_ = false;
   explicit_port_mapping_ = false;
   compress_routing_ = false;
-  print_top_testbench_ = false;
-  print_formal_verification_top_netlist_ = false;
-  reference_verilog_file_path_.clear();
   print_user_defined_template_ = false;
   verbose_output_ = false;
 }
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h
index 38ef05f9a..22c9b51c5 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.h
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h
@@ -23,10 +23,6 @@ class FabricVerilogOption {
     bool include_signal_init() const;
     bool explicit_port_mapping() const;
     bool compress_routing() const;
-    bool print_top_testbench() const;
-    bool print_formal_verification_top_netlist() const;
-    bool print_autocheck_top_testbench() const;
-    std::string reference_verilog_file_path() const;
     bool print_user_defined_template() const;
     bool verbose_output() const;
   public: /* Public mutators */
@@ -36,9 +32,6 @@ class FabricVerilogOption {
     void set_include_signal_init(const bool& enabled);
     void set_explicit_port_mapping(const bool& enabled);
     void set_compress_routing(const bool& enabled);
-    void set_print_top_testbench(const bool& enabled);
-    void set_print_formal_verification_top_netlist(const bool& enabled);
-    void set_print_autocheck_top_testbench(const std::string& reference_verilog_file_path);
     void set_print_user_defined_template(const bool& enabled);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
@@ -48,10 +41,6 @@ class FabricVerilogOption {
     bool include_timing_;
     bool explicit_port_mapping_;
     bool compress_routing_;
-    bool print_top_testbench_;
-    bool print_formal_verification_top_netlist_;
-    /* print_autocheck_top_testbench will be enabled when reference file path is not empty */
-    std::string reference_verilog_file_path_;
     bool print_user_defined_template_;
     bool verbose_output_;
 };