Moved spice and verilog netlist folder location
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@ -5,7 +5,7 @@
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//------ Include defines: preproc flags -----
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`include "GENERATED_DIR_KEYWORD/SRC/fpga_defines.v"
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`include "./SRC/fpga_defines.v"
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module static_dff (
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/* Global ports go first */
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input set, // set input
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@ -0,0 +1,43 @@
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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./openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml \
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./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
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--top_module s298 \
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--power \
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--power_tech ./openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml \
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--min_route_chan_width 1.3 \
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--vpr_fpga_verilog \
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--vpr_fpga_verilog_dir ./SRC \
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--vpr_fpga_x2p_rename_illegal_port \
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--vpr_fpga_verilog_print_autocheck_top_testbench
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# \
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# --end_flow_with_test \
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# --vpr_fpga_verilog_print_autocheck_top_testbench \
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# --vpr_fpga_verilog_include_icarus_simulator \
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# --vpr_fpga_verilog_formal_verification_top_netlist
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/vpr',
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/tmp/arch/k6_N10_rram_memory_bank_SC_winbond90.xml', 's298_ace_corrected_out.blif'
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# '--net_file'
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# 's298_vpr.net'
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# '--place_file'
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# 's298_vpr.place'
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# '--route_file'
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# 's298_vpr.route'
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# '--full_stats'
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# '--nodisp'
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# '--power'
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# '--activity_file'
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# 's298_ace_out.act'
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# '--tech_properties'
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# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml'
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# '--fpga_verilog'
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# '--fpga_verilog_dir'
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# './SRC'
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# '--fpga_verilog_print_autocheck_top_testbench'
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# 's298_output_verilog.v'
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# '--fpga_verilog_print_formal_verification_top_netlist'
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# '--fpga_verilog_include_icarus_simulator'
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# '--fpga_x2p_rename_illegal_port'
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@ -1,33 +0,0 @@
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#!/bin/bash
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echo "#################################################"
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echo "The current shell environment is the following:"
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echo $0
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echo "#################################################"
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# Example of how to run vprset circuit_name = pip_add
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#set circuit_name = pip_add
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circuit_name=sync_4bits_add
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circuit_blif=${PWD}/Circuits/${circuit_name}.blif
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arch_file=${PWD}/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
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arch_file_template=${PWD}/ARCH/k6_N10_sram_chain_HC_template.xml
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circuit_act=${PWD}/Circuits/${circuit_name}.act
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circuit_verilog=${PWD}/Circuits/${circuit_name}.v
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spice_output=${PWD}/spice_demo
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verilog_output=${PWD}/verilog_demo
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modelsim_ini=/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
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openfpga_path=${PWD}/../..
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# Make sure a clean start
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rm -rf ${spice_output}
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rm -rf ${verilog_output}
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echo "*******************************"
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echo "THIS SCRIPT NEEDS TO BE SOURCED"
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echo "source ./go.sh"
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echo "*******************************"
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sed "s:OPENFPGAPATH:${openfpga_path}:g" ${arch_file_template} > ${arch_file}
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# Pack, place, and route a heterogeneous FPGA
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# Packing uses the AAPack algorithm
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./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench
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@ -1,41 +0,0 @@
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#!/bin/bash
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# Example of how to run vpr
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# Set variables
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# For FPGA-Verilog ONLY
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benchmark="test_modes"
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OpenFPGA_path="OPENFPGAPATHKEYWORD"
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirpath="$PWD"
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tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
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# VPR critical inputs
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template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
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arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
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blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
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act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
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verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
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vpr_route_chan_width="300"
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fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
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ff_path="$vpr_path/VerilogNetlists/ff.v"
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new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
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ff_keyword="GENERATED_DIR_KEYWORD"
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ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
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arch_ff_keyword="FFPATHKEYWORD"
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# Remove previous designs
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rm -rf $verilog_output_dirpath/$verilog_output_dirname
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mkdir -p ${OpenFPGA_path}/fpga_flow/arch/generated
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
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perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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cd -
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# Run VPR
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echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
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cd -
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