Moved spice and verilog netlist folder location

openfpga_flow/VerilogNetlists/ff.v

@@ -5,15 +5,15 @@
 // Coder       : Xifan TANG
 //-----------------------------------------------------
 //------ Include defines: preproc flags -----
-`include "GENERATED_DIR_KEYWORD/SRC/fpga_defines.v"
+`include "./SRC/fpga_defines.v"
 module static_dff (
 /* Global ports go first */
 input set,     // set input
-input reset, // Reset input 
+input reset, // Reset input
 input clk, // Clock Input
 /* Local ports follow */
 input D, // Data Input
-output Q // Q output 
+output Q // Q output
 );
 //------------Internal Variables--------
 reg q_reg;
@@ -29,7 +29,7 @@ end else begin
 end
 
 // Wire q_reg to Q
-assign Q = q_reg; 
+assign Q = q_reg;
 
 endmodule //End Of Module static_dff
 
@@ -42,12 +42,12 @@ endmodule //End Of Module static_dff
 module sc_dff (
 /* Global ports go first */
 input set,     // set input
-input reset, // Reset input 
+input reset, // Reset input
 input clk, // Clock Input
 /* Local ports follow */
 input D, // Data Input
-output Q, // Q output 
+output Q, // Q output
-output Qb // Q output 
+output Qb // Q output
 );
 //------------Internal Variables--------
 reg q_reg;
@@ -63,7 +63,7 @@ end else begin
 end
 
 // Wire q_reg to Q
-assign Q = q_reg; 
+assign Q = q_reg;
 assign Qb = ~Q;
 
 endmodule //End Of Module static_dff
@@ -76,13 +76,13 @@ endmodule //End Of Module static_dff
 //-----------------------------------------------------
 module sc_dff_compact (
 /* Global ports go first */
-input reset, // Reset input 
+input reset, // Reset input
 //input set,     // set input
 input clk, // Clock Input
 /* Local ports follow */
 input D, // Data Input
-output Q, // Q output 
+output Q, // Q output
-output Qb // Q output 
+output Qb // Q output
 );
 //------------Internal Variables--------
 reg q_reg;
@@ -98,16 +98,16 @@ end else begin
 end
 /*
 // Wire q_reg to Q
-assign Q = q_reg; 
+assign Q = q_reg;
 assign Qb = ~Q;
 */
 
 `ifndef ENABLE_FORMAL_VERIFICATION
 // Wire q_reg to Q
-assign Q = q_reg; 
+assign Q = q_reg;
 assign Qb = ~q_reg;
 `else
-assign Q = 1'bZ; 
+assign Q = 1'bZ;
 assign Qb = !Q;
 `endif
 

run_test.sh

@@ -0,0 +1,43 @@
+python3.5 openfpga_flow/scripts/run_fpga_flow.py \
+./openfpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml \
+./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
+--top_module s298 \
+--power \
+--power_tech ./openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml \
+--min_route_chan_width 1.3 \
+--vpr_fpga_verilog \
+--vpr_fpga_verilog_dir ./SRC \
+--vpr_fpga_x2p_rename_illegal_port \
+--vpr_fpga_verilog_print_autocheck_top_testbench
+
+
+# \
+# --end_flow_with_test \
+# --vpr_fpga_verilog_print_autocheck_top_testbench \
+# --vpr_fpga_verilog_include_icarus_simulator \
+# --vpr_fpga_verilog_formal_verification_top_netlist
+
+
+# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/vpr7_x2p/vpr/vpr',
+# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/tmp/arch/k6_N10_rram_memory_bank_SC_winbond90.xml', 's298_ace_corrected_out.blif'
+# '--net_file'
+# 's298_vpr.net'
+# '--place_file'
+# 's298_vpr.place'
+# '--route_file'
+# 's298_vpr.route'
+# '--full_stats'
+# '--nodisp'
+# '--power'
+# '--activity_file'
+# 's298_ace_out.act'
+# '--tech_properties'
+# '/research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/openfpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml'
+# '--fpga_verilog'
+# '--fpga_verilog_dir'
+# './SRC'
+# '--fpga_verilog_print_autocheck_top_testbench'
+# 's298_output_verilog.v'
+# '--fpga_verilog_print_formal_verification_top_netlist'
+# '--fpga_verilog_include_icarus_simulator'
+# '--fpga_x2p_rename_illegal_port'

vpr7_x2p/vpr/go_ganesh.sh

@@ -1,33 +0,0 @@
-#!/bin/bash
-echo "#################################################"
-echo "The current shell environment is the following:"
-echo $0
-echo "#################################################"
-
-# Example of how to run vprset circuit_name = pip_add
-#set circuit_name = pip_add
-circuit_name=sync_4bits_add
-circuit_blif=${PWD}/Circuits/${circuit_name}.blif
-arch_file=${PWD}/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
-arch_file_template=${PWD}/ARCH/k6_N10_sram_chain_HC_template.xml
-circuit_act=${PWD}/Circuits/${circuit_name}.act
-circuit_verilog=${PWD}/Circuits/${circuit_name}.v
-spice_output=${PWD}/spice_demo 
-verilog_output=${PWD}/verilog_demo 
-modelsim_ini=/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
-openfpga_path=${PWD}/../..
-
-# Make sure a clean start
-rm -rf ${spice_output}
-rm -rf ${verilog_output}
-
-echo "*******************************"
-echo "THIS SCRIPT NEEDS TO BE SOURCED"
-echo "source ./go.sh"
-echo "*******************************"
-
-sed "s:OPENFPGAPATH:${openfpga_path}:g" ${arch_file_template} > ${arch_file} 
-
-# Pack, place, and route a heterogeneous FPGA
-# Packing uses the AAPack algorithm
-./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench

vpr7_x2p/vpr/regression_verilog.sh

@@ -1,41 +0,0 @@
-#!/bin/bash
-# Example of how to run vpr
-
-# Set variables
-# For FPGA-Verilog ONLY 
-benchmark="test_modes"
-OpenFPGA_path="OPENFPGAPATHKEYWORD"
-verilog_output_dirname="${benchmark}_Verilog"
-verilog_output_dirpath="$PWD"
-tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
-# VPR critical inputs
-template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
-arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
-blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" 
-act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
-verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
-vpr_route_chan_width="300"
-fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
-ff_path="$vpr_path/VerilogNetlists/ff.v"
-new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
-ff_keyword="GENERATED_DIR_KEYWORD"
-ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
-arch_ff_keyword="FFPATHKEYWORD"
-
-# Remove previous designs
-rm -rf $verilog_output_dirpath/$verilog_output_dirname
-
-mkdir -p ${OpenFPGA_path}/fpga_flow/arch/generated
-
-cd $fpga_flow_scripts
-perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
-perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
-cd -
-
-# Run VPR  
-echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
-./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping
-
-cd $fpga_flow_scripts
-perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
-cd -