[core] support perimeter cb when identify pins of I/Os tiles

openfpga/src/base/openfpga_pb_pin_fixup.cpp

@@ -60,7 +60,7 @@ static void update_cluster_pin_with_post_routing_results(
       rr_node_type = IPIN;
     }
     std::vector<e_side> pin_sides =
-      find_physical_tile_pin_side(physical_tile, physical_pin, border_side);
+      find_physical_tile_pin_side(physical_tile, physical_pin, border_side, device_ctx.arch->perimeter_cb);
     /* As some grid has height/width offset, we may not have the pin on any side
      */
     if (0 == pin_sides.size()) {

openfpga/src/fabric/build_device_module.cpp

@@ -142,7 +142,9 @@ int build_device_module_graph(
     openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol,
     sram_model, fabric_tile, name_module_using_index, frame_view,
     compress_routing, duplicate_grid_pin, fabric_key,
-    generate_random_fabric_key, group_config_block, verbose);
+    generate_random_fabric_key, group_config_block,
+    vpr_device_ctx.arch->perimeter_cb,
+    verbose);
 
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;

openfpga/src/fabric/build_top_module.cpp

@@ -58,7 +58,9 @@ int build_top_module(
   const bool& name_module_using_index, const bool& frame_view,
   const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
   const FabricKey& fabric_key, const bool& generate_random_fabric_key,
-  const bool& group_config_block, const bool& verbose) {
+  const bool& group_config_block,
+  const bool& perimeter_cb,
+  const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Build FPGA fabric module");
 
   int status = CMD_EXEC_SUCCESS;
@@ -79,7 +81,7 @@ int build_top_module(
       rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
       rr_graph, device_rr_gsb, tile_direct, arch_direct, config_protocol,
       sram_model, frame_view, compact_routing_hierarchy, duplicate_grid_pin,
-      fabric_key, group_config_block, verbose);
+      fabric_key, group_config_block, perimeter_cb, verbose);
   } else {
     /* Build the tile instances under the top module */
     status = build_top_module_tile_child_instances(
@@ -87,7 +89,7 @@ int build_top_module(
       rr_clock_lookup, vpr_device_annotation, grids, layer, tile_annotation,
       rr_graph, device_rr_gsb, tile_direct, arch_direct, fabric_tile,
       config_protocol, sram_model, fabric_key, group_config_block,
-      name_module_using_index, frame_view, verbose);
+      name_module_using_index, perimeter_cb, frame_view, verbose);
   }
 
   if (status != CMD_EXEC_SUCCESS) {

openfpga/src/fabric/build_top_module.h

@@ -45,7 +45,9 @@ int build_top_module(
   const bool& name_module_using_index, const bool& frame_view,
   const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin,
   const FabricKey& fabric_key, const bool& generate_random_fabric_key,
-  const bool& group_config_block, const bool& verbose);
+  const bool& group_config_block,
+  const bool& perimeter_cb,
+  const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fabric/build_top_module_child_fine_grained_instance.cpp

@@ -454,7 +454,9 @@ int build_top_module_fine_grained_child_instances(
   const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
   const bool& frame_view, const bool& compact_routing_hierarchy,
   const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const bool& group_config_block, const bool& verbose) {
+  const bool& group_config_block,
+  const bool& perimeter_cb,
+  const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
   std::map<t_rr_type, vtr::Matrix<size_t>> cb_instance_ids;
 
@@ -501,7 +503,7 @@ int build_top_module_fine_grained_child_instances(
   status = add_top_module_global_ports_from_grid_modules(
     module_manager, top_module, tile_annotation, vpr_device_annotation, grids,
     layer, rr_graph, device_rr_gsb, cb_instance_ids, grid_instance_ids,
-    clk_ntwk, rr_clock_lookup);
+    clk_ntwk, rr_clock_lookup, perimeter_cb);
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;
   }

openfpga/src/fabric/build_top_module_child_fine_grained_instance.h

@@ -44,7 +44,9 @@ int build_top_module_fine_grained_child_instances(
   const ConfigProtocol& config_protocol, const CircuitModelId& sram_model,
   const bool& frame_view, const bool& compact_routing_hierarchy,
   const bool& duplicate_grid_pin, const FabricKey& fabric_key,
-  const bool& group_config_block, const bool& verbose);
+  const bool& group_config_block,
+  const bool& perimeter_cb,
+  const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/fabric/build_top_module_child_tile_instance.cpp

@@ -1295,7 +1295,7 @@ static int build_top_module_global_net_for_given_tile_module(
   const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
   const size_t& layer, const vtr::Point<size_t>& grid_coordinate,
   const e_side& border_side, const vtr::Matrix<size_t>& tile_instance_ids,
-  const FabricTile& fabric_tile) {
+  const FabricTile& fabric_tile, const bool& perimeter_cb) {
   /* Get the tile module and instance */
   FabricTileId curr_fabric_tile_id =
     fabric_tile.find_tile_by_pb_coordinate(grid_coordinate);
@@ -1392,7 +1392,7 @@ static int build_top_module_global_net_for_given_tile_module(
         size_t grid_pin_height =
           physical_tile->pin_height_offset[grid_pin_index];
         std::vector<e_side> pin_sides = find_physical_tile_pin_side(
-          physical_tile, grid_pin_index, border_side);
+          physical_tile, grid_pin_index, border_side, perimeter_cb);
 
         BasicPort grid_pin_info =
           vpr_device_annotation.physical_tile_pin_port_info(physical_tile,
@@ -1452,7 +1452,7 @@ static int build_top_module_global_net_from_tile_modules(
   const TileGlobalPortId& tile_global_port,
   const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
   const size_t& layer, const vtr::Matrix<size_t>& tile_instance_ids,
-  const FabricTile& fabric_tile) {
+  const FabricTile& fabric_tile, const bool& perimeter_cb) {
   int status = CMD_EXEC_SUCCESS;
 
   std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
@@ -1531,7 +1531,7 @@ static int build_top_module_global_net_from_tile_modules(
           module_manager, top_module, top_module_port, tile_annotation,
           tile_global_port, tile_port, vpr_device_annotation, grids, layer,
           vtr::Point<size_t>(ix, iy), NUM_SIDES, tile_instance_ids,
-          fabric_tile);
+          fabric_tile, perimeter_cb);
         if (CMD_EXEC_FATAL_ERROR == status) {
           return status;
         }
@@ -1578,7 +1578,7 @@ static int build_top_module_global_net_from_tile_modules(
         status = build_top_module_global_net_for_given_tile_module(
           module_manager, top_module, top_module_port, tile_annotation,
           tile_global_port, tile_port, vpr_device_annotation, grids, layer,
-          io_coordinate, io_side, tile_instance_ids, fabric_tile);
+          io_coordinate, io_side, tile_instance_ids, fabric_tile, perimeter_cb);
         if (CMD_EXEC_FATAL_ERROR == status) {
           return status;
         }
@@ -1600,7 +1600,7 @@ static int add_top_module_global_ports_from_tile_modules(
   const size_t& layer, const RRGraphView& rr_graph,
   const DeviceRRGSB& device_rr_gsb,
   const vtr::Matrix<size_t>& tile_instance_ids, const FabricTile& fabric_tile,
-  const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) {
+  const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup, const bool& perimeter_cb) {
   int status = CMD_EXEC_SUCCESS;
 
   /* Add the global ports which are NOT yet added to the top-level module
@@ -1657,7 +1657,7 @@ static int add_top_module_global_ports_from_tile_modules(
       status = build_top_module_global_net_from_tile_modules(
         module_manager, top_module, top_module_port, tile_annotation,
         tile_global_port, vpr_device_annotation, grids, layer,
-        tile_instance_ids, fabric_tile);
+        tile_instance_ids, fabric_tile, perimeter_cb);
     }
     if (status == CMD_EXEC_FATAL_ERROR) {
       return status;
@@ -1905,6 +1905,7 @@ int build_top_module_tile_child_instances(
   const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricKey& fabric_key,
   const bool& group_config_block, const bool& name_module_using_index,
+  const bool& perimeter_cb,
   const bool& frame_view, const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
   vtr::Matrix<size_t> tile_instance_ids;
@@ -1942,7 +1943,7 @@ int build_top_module_tile_child_instances(
   status = add_top_module_global_ports_from_tile_modules(
     module_manager, top_module, tile_annotation, vpr_device_annotation, grids,
     layer, rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk,
-    rr_clock_lookup);
+    rr_clock_lookup, perimeter_cb);
   if (CMD_EXEC_FATAL_ERROR == status) {
     return status;
   }

openfpga/src/fabric/build_top_module_child_tile_instance.h

@@ -44,6 +44,7 @@ int build_top_module_tile_child_instances(
   const FabricTile& fabric_tile, const ConfigProtocol& config_protocol,
   const CircuitModelId& sram_model, const FabricKey& fabric_key,
   const bool& group_config_block, const bool& name_module_using_index,
+  const bool& perimeter_cb,
   const bool& frame_view, const bool& verbose);
 
 } /* end namespace openfpga */

openfpga/src/fabric/build_top_module_connection.cpp

@@ -956,7 +956,8 @@ static int build_top_module_global_net_for_given_grid_module(
   const BasicPort& tile_port_to_connect,
   const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
   const size_t& layer, const vtr::Point<size_t>& grid_coordinate,
-  const e_side& border_side, const vtr::Matrix<size_t>& grid_instance_ids) {
+  const e_side& border_side, const vtr::Matrix<size_t>& grid_instance_ids,
+  const bool& perimeter_cb) {
   t_physical_tile_type_ptr physical_tile = grids.get_physical_type(
     t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer));
   /* Find the module name for this type of grid */
@@ -1033,7 +1034,7 @@ static int build_top_module_global_net_for_given_grid_module(
         size_t grid_pin_height =
           physical_tile->pin_height_offset[grid_pin_index];
         std::vector<e_side> pin_sides = find_physical_tile_pin_side(
-          physical_tile, grid_pin_index, border_side);
+          physical_tile, grid_pin_index, border_side, perimeter_cb);
 
         BasicPort grid_pin_info =
           vpr_device_annotation.physical_tile_pin_port_info(physical_tile,
@@ -1091,7 +1092,8 @@ static int build_top_module_global_net_from_grid_modules(
   const ModulePortId& top_module_port, const TileAnnotation& tile_annotation,
   const TileGlobalPortId& tile_global_port,
   const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
-  const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids) {
+  const size_t& layer, const vtr::Matrix<size_t>& grid_instance_ids,
+  const bool& perimeter_cb) {
   int status = CMD_EXEC_SUCCESS;
 
   std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
@@ -1169,7 +1171,7 @@ static int build_top_module_global_net_from_grid_modules(
         status = build_top_module_global_net_for_given_grid_module(
           module_manager, top_module, top_module_port, tile_annotation,
           tile_global_port, tile_port, vpr_device_annotation, grids, layer,
-          vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids);
+          vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids, perimeter_cb);
         if (CMD_EXEC_FATAL_ERROR == status) {
           return status;
         }
@@ -1216,7 +1218,7 @@ static int build_top_module_global_net_from_grid_modules(
         status = build_top_module_global_net_for_given_grid_module(
           module_manager, top_module, top_module_port, tile_annotation,
           tile_global_port, tile_port, vpr_device_annotation, grids, layer,
-          io_coordinate, io_side, grid_instance_ids);
+          io_coordinate, io_side, grid_instance_ids, perimeter_cb);
         if (CMD_EXEC_FATAL_ERROR == status) {
           return status;
         }
@@ -1317,7 +1319,8 @@ int add_top_module_global_ports_from_grid_modules(
   const DeviceRRGSB& device_rr_gsb,
   const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
   const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
-  const RRClockSpatialLookup& rr_clock_lookup) {
+  const RRClockSpatialLookup& rr_clock_lookup,
+  const bool& perimeter_cb) {
   int status = CMD_EXEC_SUCCESS;
 
   /* Add the global ports which are NOT yet added to the top-level module
@@ -1382,7 +1385,7 @@ int add_top_module_global_ports_from_grid_modules(
       status = build_top_module_global_net_from_grid_modules(
         module_manager, top_module, top_module_port, tile_annotation,
         tile_global_port, vpr_device_annotation, grids, layer,
-        grid_instance_ids);
+        grid_instance_ids, perimeter_cb);
     }
     if (status == CMD_EXEC_FATAL_ERROR) {
       return status;

openfpga/src/fabric/build_top_module_connection.h

@@ -42,7 +42,8 @@ int add_top_module_global_ports_from_grid_modules(
   const DeviceRRGSB& device_rr_gsb,
   const std::map<t_rr_type, vtr::Matrix<size_t>>& cb_instance_ids,
   const vtr::Matrix<size_t>& grid_instance_ids, const ClockNetwork& clk_ntwk,
-  const RRClockSpatialLookup& rr_clock_lookup);
+  const RRClockSpatialLookup& rr_clock_lookup,
+  const bool& perimeter_cb);
 
 void add_top_module_nets_prog_clock(ModuleManager& module_manager,
                                     const ModuleId& top_module,

openfpga/src/utils/openfpga_physical_tile_utils.cpp

@@ -27,7 +27,7 @@ namespace openfpga {
  *******************************************************************/
 std::vector<e_side> find_physical_tile_pin_side(
   t_physical_tile_type_ptr physical_tile, const int& physical_pin,
-  const e_side& border_side) {
+  const e_side& border_side, const bool& perimeter_cb) {
   std::vector<e_side> pin_sides;
   for (const e_side& side_cand : {TOP, RIGHT, BOTTOM, LEFT}) {
     int pin_width_offset = physical_tile->pin_width_offset[physical_pin];
@@ -40,17 +40,20 @@ std::vector<e_side> find_physical_tile_pin_side(
 
   /* For regular grid, we should have pin only one side!
    * I/O grids: VPR creates the grid with duplicated pins on every side
-   * but the expected side (only used side) will be opposite side of the border
+   * - In regular cases: the expected side (only used side) will be on the opposite to the border
    * side!
+   * - When perimeter cb is on, the expected sides can be on any sides except the border side. But we only expect 1 side
    */
   if (NUM_SIDES == border_side) {
     VTR_ASSERT(1 == pin_sides.size());
-  } else {
+  } else if (!perimeter_cb) {
     SideManager side_manager(border_side);
     VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), pin_sides.end(),
                                             side_manager.get_opposite()));
     pin_sides.clear();
     pin_sides.push_back(side_manager.get_opposite());
+  } else {
+    VTR_ASSERT(1 == pin_sides.size() && pin_sides[0] != border_side);
   }
 
   return pin_sides;

openfpga/src/utils/openfpga_physical_tile_utils.h

@@ -20,7 +20,7 @@ namespace openfpga {
 
 std::vector<e_side> find_physical_tile_pin_side(
   t_physical_tile_type_ptr physical_tile, const int& physical_pin,
-  const e_side& border_side);
+  const e_side& border_side, const bool& perimeter_cb);
 
 float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin);