[core] code format

libs/libclkarchopenfpga/src/base/clock_network.cpp

@@ -32,8 +32,10 @@ ClockNetwork::clock_tree_range ClockNetwork::trees() const {
   return vtr::make_range(tree_ids_.begin(), tree_ids_.end());
 }
 
-ClockNetwork::clock_internal_driver_range ClockNetwork::internal_drivers() const {
+ClockNetwork::clock_internal_driver_range ClockNetwork::internal_drivers()
-  return vtr::make_range(internal_driver_ids_.begin(), internal_driver_ids_.end());
+  const {
+  return vtr::make_range(internal_driver_ids_.begin(),
+                         internal_driver_ids_.end());
 }
 
 std::vector<ClockLevelId> ClockNetwork::levels(
@@ -329,14 +331,16 @@ vtr::Point<int> ClockNetwork::spine_switch_point(
   return spine_switch_coords_[spine_id][size_t(switch_point_id)];
 }
 
-std::vector<ClockInternalDriverId> ClockNetwork::spine_switch_point_internal_drivers(
+std::vector<ClockInternalDriverId>
+ClockNetwork::spine_switch_point_internal_drivers(
   const ClockSpineId& spine_id,
   const ClockSwitchPointId& switch_point_id) const {
   VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id));
   return spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)];
 }
 
-std::string ClockNetwork::internal_driver_port(const ClockInternalDriverId& int_driver_id) const {
+std::string ClockNetwork::internal_driver_port(
+  const ClockInternalDriverId& int_driver_id) const {
   VTR_ASSERT(valid_internal_driver_id(int_driver_id));
   return internal_driver_ports_[int_driver_id];
 }
@@ -389,7 +393,8 @@ std::vector<std::string> ClockNetwork::tree_flatten_taps(
   return flatten_taps;
 }
 
-std::vector<std::string> ClockNetwork::flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const {
+std::vector<std::string> ClockNetwork::flatten_internal_driver_port(
+  const ClockInternalDriverId& int_driver_id) const {
   std::vector<std::string> flatten_taps;
   std::string tap_name = internal_driver_port(int_driver_id);
   StringToken tokenizer(tap_name);
@@ -598,9 +603,9 @@ void ClockNetwork::set_spine_track_type(const ClockSpineId& spine_id,
   spine_track_types_[spine_id] = type;
 }
 
-ClockSwitchPointId ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id,
+ClockSwitchPointId ClockNetwork::add_spine_switch_point(
-                                          const ClockSpineId& drive_spine_id,
+  const ClockSpineId& spine_id, const ClockSpineId& drive_spine_id,
-                                          const vtr::Point<int>& coord) {
+  const vtr::Point<int>& coord) {
   VTR_ASSERT(valid_spine_id(spine_id));
   VTR_ASSERT(valid_spine_id(drive_spine_id));
   spine_switch_points_[spine_id].push_back(drive_spine_id);
@@ -621,23 +626,26 @@ ClockSwitchPointId ClockNetwork::add_spine_switch_point(const ClockSpineId& spin
   return ClockSwitchPointId(spine_switch_points_[spine_id].size() - 1);
 }
 
-ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(const ClockSpineId& spine_id,
+ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(
-                                                          const ClockSwitchPointId& switch_point_id,
+  const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id,
-                                                          const std::string& int_driver_port) {
+  const std::string& int_driver_port) {
   VTR_ASSERT(valid_spine_id(spine_id));
   VTR_ASSERT(valid_spine_switch_point_id(spine_id, switch_point_id));
   /* Find any existing id for the driver port */
   for (ClockInternalDriverId int_driver_id : internal_driver_ids_) {
     if (internal_driver_ports_[int_driver_id] == int_driver_port) {
-      spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(int_driver_id);
+      spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)]
+        .push_back(int_driver_id);
       return int_driver_id;
     }
   }
   /* Reaching here, no existing id can be reused, create a new one */
-  ClockInternalDriverId int_driver_id = ClockInternalDriverId(internal_driver_ids_.size());
+  ClockInternalDriverId int_driver_id =
+    ClockInternalDriverId(internal_driver_ids_.size());
   internal_driver_ids_.push_back(int_driver_id);
   internal_driver_ports_.push_back(int_driver_port);
-  spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(int_driver_id);
+  spine_switch_internal_drivers_[spine_id][size_t(switch_point_id)].push_back(
+    int_driver_id);
   return int_driver_id;
 }
 
@@ -793,7 +801,8 @@ bool ClockNetwork::valid_tree_id(const ClockTreeId& tree_id) const {
          (tree_id == tree_ids_[tree_id]);
 }
 
-bool ClockNetwork::valid_internal_driver_id(const ClockInternalDriverId& int_driver_id) const {
+bool ClockNetwork::valid_internal_driver_id(
+  const ClockInternalDriverId& int_driver_id) const {
   return (size_t(int_driver_id) < internal_driver_ids_.size()) &&
          (int_driver_id == internal_driver_ids_[int_driver_id]);
 }

libs/libclkarchopenfpga/src/base/clock_network.h

@@ -42,10 +42,12 @@ class ClockNetwork {
     clock_tree_iterator;
   /* Create range */
   typedef vtr::Range<clock_tree_iterator> clock_tree_range;
-  typedef vtr::vector<ClockInternalDriverId, ClockInternalDriverId>::const_iterator
+  typedef vtr::vector<ClockInternalDriverId,
+                      ClockInternalDriverId>::const_iterator
     clock_internal_driver_iterator;
   /* Create range */
-  typedef vtr::Range<clock_internal_driver_iterator> clock_internal_driver_range;
+  typedef vtr::Range<clock_internal_driver_iterator>
+    clock_internal_driver_range;
 
  public: /* Constructors */
   ClockNetwork();
@@ -124,8 +126,10 @@ class ClockNetwork {
   std::vector<ClockInternalDriverId> spine_switch_point_internal_drivers(
     const ClockSpineId& spine_id,
     const ClockSwitchPointId& switch_point_id) const;
-  std::string internal_driver_port(const ClockInternalDriverId& int_driver_id) const;
+  std::string internal_driver_port(
-  std::vector<std::string> flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const;
+    const ClockInternalDriverId& int_driver_id) const;
+  std::vector<std::string> flatten_internal_driver_port(
+    const ClockInternalDriverId& int_driver_id) const;
 
   /* Return the original list of tap pins that is in storage; useful for parsers
    */
@@ -184,11 +188,11 @@ class ClockNetwork {
   void set_spine_track_type(const ClockSpineId& spine_id,
                             const t_rr_type& type);
   ClockSwitchPointId add_spine_switch_point(const ClockSpineId& spine_id,
-                              const ClockSpineId& drive_spine_id,
+                                            const ClockSpineId& drive_spine_id,
-                              const vtr::Point<int>& coord);
+                                            const vtr::Point<int>& coord);
-  ClockInternalDriverId add_spine_switch_point_internal_driver(const ClockSpineId& spine_id,
+  ClockInternalDriverId add_spine_switch_point_internal_driver(
-                                              const ClockSwitchPointId& switch_point_id,
+    const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id,
-							                  const std::string& internal_driver_port);
+    const std::string& internal_driver_port);
   void add_tree_tap(const ClockTreeId& tree_id, const std::string& pin_name);
   /* Build internal links between clock tree, spines etc. This is also an
    * validator to verify the correctness of the clock network. Must run before
@@ -198,7 +202,8 @@ class ClockNetwork {
  public: /* Public invalidators/validators */
   /* Show if the tree id is a valid for data queries */
   bool valid_tree_id(const ClockTreeId& tree_id) const;
-  bool valid_internal_driver_id(const ClockInternalDriverId& int_driver_id) const;
+  bool valid_internal_driver_id(
+    const ClockInternalDriverId& int_driver_id) const;
   /* Show if the level id is a valid for a given tree */
   bool valid_level_id(const ClockTreeId& tree_id,
                       const ClockLevelId& lvl_id) const;
@@ -260,13 +265,15 @@ class ClockNetwork {
   vtr::vector<ClockSpineId, t_rr_type> spine_track_types_;
   vtr::vector<ClockSpineId, std::vector<ClockSpineId>> spine_switch_points_;
   vtr::vector<ClockSpineId, std::vector<vtr::Point<int>>> spine_switch_coords_;
-  vtr::vector<ClockSpineId, std::vector<std::vector<ClockInternalDriverId>>> spine_switch_internal_drivers_;
+  vtr::vector<ClockSpineId, std::vector<std::vector<ClockInternalDriverId>>>
+    spine_switch_internal_drivers_;
   vtr::vector<ClockSpineId, ClockSpineId> spine_parents_;
   vtr::vector<ClockSpineId, std::vector<ClockSpineId>> spine_children_;
   vtr::vector<ClockSpineId, ClockTreeId> spine_parent_trees_;
 
   /* Basic Information about internal drivers */
-  vtr::vector<ClockInternalDriverId, ClockInternalDriverId> internal_driver_ids_;
+  vtr::vector<ClockInternalDriverId, ClockInternalDriverId>
+    internal_driver_ids_;
   vtr::vector<ClockInternalDriverId, std::string> internal_driver_ports_;
 
   /* Default routing resource */

libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h

@@ -22,8 +22,10 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y";
 constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type";
 constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction";
 constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point";
-constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = "internal_driver";
+constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME =
-constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN = "tile_pin";
+  "internal_driver";
+constexpr const char*
+  XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN = "tile_pin";
 constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_TAP = "tap";
 constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_X = "x";
 constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y = "y";

libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp

@@ -61,17 +61,20 @@ static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps,
  *******************************************************************/
 static void read_xml_clock_spine_switch_point_internal_driver(
   pugi::xml_node& xml_int_driver, const pugiutil::loc_data& loc_data,
-  ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id) {
+  ClockNetwork& clk_ntwk, const ClockSpineId& spine_id,
+  const ClockSwitchPointId& switch_point_id) {
   if (!clk_ntwk.valid_spine_id(spine_id)) {
     archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_int_driver),
                    "Invalid id of a clock spine!\n");
   }
 
   std::string int_driver_port_name =
-    get_attribute(xml_int_driver, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN,
+    get_attribute(
-                  loc_data)
+      xml_int_driver,
+      XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, loc_data)
       .as_string();
-  clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id, int_driver_port_name);
+  clk_ntwk.add_spine_switch_point_internal_driver(spine_id, switch_point_id,
+                                                  int_driver_port_name);
 }
 
 /********************************************************************
@@ -108,16 +111,16 @@ static void read_xml_clock_spine_switch_point(
                             XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, loc_data)
                 .as_int();
 
-  ClockSwitchPointId switch_point_id = clk_ntwk.add_spine_switch_point(spine_id, tap_spine_id,
+  ClockSwitchPointId switch_point_id = clk_ntwk.add_spine_switch_point(
-                                                                       vtr::Point<int>(tap_x, tap_y));
+    spine_id, tap_spine_id, vtr::Point<int>(tap_x, tap_y));
 
   /* Add internal drivers if possible */
   for (pugi::xml_node xml_int_driver : xml_switch_point.children()) {
     /* Error out if the XML child has an invalid name! */
     if (xml_int_driver.name() ==
         std::string(XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME)) {
-      read_xml_clock_spine_switch_point_internal_driver(xml_int_driver, loc_data, clk_ntwk,
+      read_xml_clock_spine_switch_point_internal_driver(
-                                                        spine_id, switch_point_id);
+        xml_int_driver, loc_data, clk_ntwk, spine_id, switch_point_id);
     } else {
       bad_tag(xml_int_driver, loc_data, xml_switch_point,
               {XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME});

libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp

@@ -61,16 +61,21 @@ static int write_xml_clock_spine_switch_point(
   write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_ATTRIBUTE_Y, coord.y());
 
   /* Optional: internal drivers */
-  if (clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id).empty()) {
+  if (clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id)
+        .empty()) {
     fp << "/>"
        << "\n";
   } else {
     fp << ">"
        << "\n";
-    for (ClockInternalDriverId int_driver_id : clk_ntwk.spine_switch_point_internal_drivers(spine_id, switch_point_id)) {
+    for (ClockInternalDriverId int_driver_id :
+         clk_ntwk.spine_switch_point_internal_drivers(spine_id,
+                                                      switch_point_id)) {
       openfpga::write_tab_to_file(fp, 4);
       fp << "<" << XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME;
-      write_xml_attribute(fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN, clk_ntwk.internal_driver_port(int_driver_id).c_str());
+      write_xml_attribute(
+        fp, XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_ATTRIBUTE_TILE_PIN,
+        clk_ntwk.internal_driver_port(int_driver_id).c_str());
       fp << "/>"
          << "\n";
     }

libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp

@@ -34,7 +34,7 @@ static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk,
  *clock network
  *******************************************************************/
 static int link_clock_network_tap_rr_switches(ClockNetwork& clk_ntwk,
-                                          const RRGraphView& rr_graph) {
+                                              const RRGraphView& rr_graph) {
   /* default tap switch id */
   std::string default_tap_switch_name = clk_ntwk.default_tap_switch_name();
   for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches();
@@ -57,7 +57,7 @@ static int link_clock_network_tap_rr_switches(ClockNetwork& clk_ntwk,
  *clock network
  *******************************************************************/
 static int link_clock_network_driver_rr_switches(ClockNetwork& clk_ntwk,
-                                          const RRGraphView& rr_graph) {
+                                                 const RRGraphView& rr_graph) {
   /* default driver switch id */
   std::string default_driver_switch_name =
     clk_ntwk.default_driver_switch_name();

openfpga/src/annotation/append_clock_rr_graph.cpp

@@ -525,8 +525,8 @@ static void add_rr_graph_block_clock_edges(
                    chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) {
               /* Create edges */
               VTR_ASSERT(rr_graph_view.valid_node(des_node));
-              rr_graph_builder.create_edge(src_node, des_node,
+              rr_graph_builder.create_edge(
-                                           clk_ntwk.default_driver_switch(), false);
+                src_node, des_node, clk_ntwk.default_driver_switch(), false);
               edge_count++;
             }
             VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n",
@@ -541,8 +541,8 @@ static void add_rr_graph_block_clock_edges(
                    itree, ClockTreePinId(ipin))) {
               /* Create edges */
               VTR_ASSERT(rr_graph_view.valid_node(des_node));
-              rr_graph_builder.create_edge(src_node, des_node,
+              rr_graph_builder.create_edge(
-                                           clk_ntwk.default_tap_switch(), false);
+                src_node, des_node, clk_ntwk.default_tap_switch(), false);
               edge_count++;
             }
             VTR_LOGV(verbose, "\tWill add %lu edges to IPINs\n",
@@ -566,8 +566,7 @@ static void try_find_and_add_clock_opin2track_node(
   std::vector<RRNodeId>& opin_nodes, const DeviceGrid& grids,
   const RRGraphView& rr_graph_view, const size_t& layer,
   const vtr::Point<int>& grid_coord, const e_side& pin_side,
-  const ClockNetwork& clk_ntwk,
+  const ClockNetwork& clk_ntwk, const ClockInternalDriverId& int_driver_id) {
-  const ClockInternalDriverId& int_driver_id) {
   t_physical_tile_type_ptr grid_type = grids.get_physical_type(
     t_physical_tile_loc(grid_coord.x(), grid_coord.y(), layer));
   for (std::string tap_pin_name :
@@ -611,11 +610,9 @@ static void try_find_and_add_clock_opin2track_node(
  *******************************************************************/
 static std::vector<RRNodeId> find_clock_opin2track_node(
   const DeviceGrid& grids, const RRGraphView& rr_graph_view,
-  const size_t& layer,
+  const size_t& layer, const vtr::Point<int>& sb_coord,
-  const vtr::Point<int>& sb_coord, 
   const ClockNetwork& clk_ntwk,
-  const std::vector<ClockInternalDriverId>& int_driver_ids
+  const std::vector<ClockInternalDriverId>& int_driver_ids) {
-) {
   std::vector<RRNodeId> opin_nodes;
   /* Find opins from
    * - Grid[x][y+1] on right and bottom sides
@@ -649,13 +646,14 @@ static std::vector<RRNodeId> find_clock_opin2track_node(
 /********************************************************************
  * Add edges between OPIN of programmable blocks and clock routing tracks
  * Note that such edges only occur at the switching points of spines
- * Different from add_rr_graph_block_clock_edges(), we follow the clock spines here
+ * Different from add_rr_graph_block_clock_edges(), we follow the clock spines
- * By expanding on switching points, internal drivers will be added
+ *here By expanding on switching points, internal drivers will be added
  *******************************************************************/
-static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
+static int add_rr_graph_opin2clk_edges(
+  RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
   const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
-  const DeviceGrid& grids, const size_t& layer,
+  const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk,
-  const ClockNetwork& clk_ntwk, const bool& verbose) {
+  const bool& verbose) {
   size_t edge_count = 0;
   for (ClockTreeId clk_tree : clk_ntwk.trees()) {
     for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) {
@@ -664,8 +662,11 @@ static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t&
       for (auto ipin : clk_ntwk.pins(clk_tree)) {
         for (ClockSwitchPointId switch_point_id :
              clk_ntwk.spine_switch_points(ispine)) {
-          if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) {
+          if (clk_ntwk
-            continue; /* We only focus on switching points containing internal drivers */
+                .spine_switch_point_internal_drivers(ispine, switch_point_id)
+                .empty()) {
+            continue; /* We only focus on switching points containing internal
+                         drivers */
           }
           size_t curr_edge_count = edge_count;
           /* Get the rr node of destination spine */
@@ -680,12 +681,16 @@ static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t&
           /* Walk through each qualified OPIN, build edges */
           vtr::Point<int> src_coord =
             clk_ntwk.spine_switch_point(ispine, switch_point_id);
-          std::vector<ClockInternalDriverId> int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id);
+          std::vector<ClockInternalDriverId> int_driver_ids =
-          for (RRNodeId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) {
+            clk_ntwk.spine_switch_point_internal_drivers(ispine,
+                                                         switch_point_id);
+          for (RRNodeId src_node : find_clock_opin2track_node(
+                 grids, rr_graph_view, layer, src_coord, clk_ntwk,
+                 int_driver_ids)) {
             /* Create edges */
             VTR_ASSERT(rr_graph_view.valid_node(des_node));
-            rr_graph_builder.create_edge(src_node, des_node,
+            rr_graph_builder.create_edge(
-                                         clk_ntwk.default_driver_switch(), false);
+              src_node, des_node, clk_ntwk.default_driver_switch(), false);
             edge_count++;
           }
           VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n",
@@ -758,7 +763,9 @@ static void add_rr_graph_clock_edges(
     }
   }
   /* Add edges between OPIN (internal driver) and clock routing tracks */
-  add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, verbose);
+  add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create,
+                              clk_rr_lookup, rr_graph_view, grids, layer,
+                              clk_ntwk, verbose);
 }
 
 /********************************************************************

openfpga/src/base/openfpga_read_arch_template.h

@@ -240,8 +240,9 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd,
     VTR_LOG_ERROR("Link clock network failed!");
     return CMD_EXEC_FATAL_ERROR;
   }
-  if (CMD_EXEC_SUCCESS != link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(),
+  if (CMD_EXEC_SUCCESS !=
-                              g_vpr_ctx.device().rr_graph)) {
+      link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(),
+                                  g_vpr_ctx.device().rr_graph)) {
     VTR_LOG_ERROR("Link clock network to routing architecture failed!");
     return CMD_EXEC_FATAL_ERROR;
   }