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reorganize and clean-up sample architecture

This commit is contained in:
tangxifan 2020-01-18 10:50:15 -07:00
parent ab1b1b7e02
commit 7a46c85cb0
1 changed files with 19 additions and 10 deletions
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29
libopenfpga/libarchopenfpga/arch/sample_arch.xml
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@ -255,9 +255,18 @@
</circuit_library> </circuit_library>
</openfpga_architecture> </openfpga_architecture>
<openfpga_simulation_setting> <openfpga_simulation_setting>
<general sim_temp="25" post="false" captab="false" fast="true"/> <clock_setting>
<monte_carlo mc_sim="false" num_mc_points="2"/> <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs"> <programming frequency="10e6"/>
</clock_setting>
<simulator_option>
<operating_condition temperature="25"/>
<output_log post="false" captab="false"/>
<accuracy type="abs" value="1e-13"/>
<runtime fast_simulation="true"/>
</simulator_option>
<monte_carlo num_simulation_points="2"/>
<measurement_setting>
<slew> <slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/> <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/> <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
@ -266,15 +275,15 @@
<rise input_thres_pct="0.5" output_thres_pct="0.5"/> <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/> <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay> </delay>
</measure> </measurement_setting>
<stimuli> <stimulus>
<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6"> <stimuli type="clock">
<rise slew_time="20e-12" slew_type="abs"/> <rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/> <fall slew_time="20e-12" slew_type="abs"/>
</clock> </stimuli>
<input> <stimuli type="input">
<rise slew_time="25e-12" slew_type="abs"/> <rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/> <fall slew_time="25e-12" slew_type="abs"/>
</input> </stimuli>
</stimuli> </stimulus>
</openfpga_simulation_setting> </openfpga_simulation_setting>