Added blif task in travis script
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@ -30,4 +30,4 @@ $SPACER
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cd -
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# python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick
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chmod 755 run_test.sh
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./run_test.sh
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python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
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@ -15,7 +15,7 @@ timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
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# arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
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arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
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arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml
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@ -41,7 +41,7 @@ vpr_fpga_verilog_print_report_timing_tcl=
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vpr_fpga_verilog_print_sdc_pnr=
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vpr_fpga_verilog_print_sdc_analysis=
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vpr_fpga_x2p_compact_routing_hierarchy=
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# end_flow_with_test=
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end_flow_with_test=
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# [SCRIPT_PARAM_2]
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