From 7a38c7dd18f8ff237a0392c2ea5b995fa4a5f884 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Sep 2022 16:42:55 -0700 Subject: [PATCH] [benchmark] add a new benchmark to test reset signal to drive both lut and ff --- .../micro_benchmark/rst_on_lut/rst_on_lut.v | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v new file mode 100644 index 000000000..25aafe763 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v @@ -0,0 +1,23 @@ +///////////////////////////////////////// +// Functionality: A register driven by a combinational logic with reset signal +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module rst_on_lut(a, b, out, clk, rst); + +input wire rst; +input wire clk; +input wire a; +input wire b; +output reg out; + +always @(rst or posedge clk) begin + if (rst) begin + out <= 0; + end else begin + out <= a & b & rst; + end +end + +endmodule