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[Flow] Yosys rewrite support

This commit is contained in:
Ganesh Gore 2021-03-08 00:35:47 -07:00
parent 67cd9a69b7
commit 7a35811430
1 changed files with 8 additions and 2 deletions
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8
openfpga_flow/scripts/run_fpga_flow.py
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@ -698,6 +698,7 @@ def run_rewrite_verilog():
"write_verilog %s" % args.top_module+"_output_verilog.v"
]
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
run_command("Yosys", "yosys_rewrite.log", command)
else:
ys_rewrite_params = {
"INPUT_BLIF": args.top_module+".blif",
@ -706,7 +707,12 @@ def run_rewrite_verilog():
for indx in range(0, len(OpenFPGAArgs), 2):
tmpVar = OpenFPGAArgs[indx][2:].upper()
ys_rewrite_params[tmpVar] = OpenFPGAArgs[indx + 1]
run_command("Yosys", "yosys_rewrite.log", command)
tmpl = Template(open(args.ys_rewrite_tmpl, encoding='utf-8').read())
with open("yosys_rewrite.ys", 'w') as archfile:
archfile.write(tmpl.safe_substitute(ys_params))
run_command("Run yosys", "yosys_rewrite_output.log",
[cad_tools["yosys_path"], 'yosys_rewrite.ys'])
def run_netlists_verification(exit_if_fail=True):