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[doc] update with example

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tangxifan 2023-06-26 12:11:00 -07:00
parent df17f43024
commit 7974ea4426
1 changed files with 35 additions and 2 deletions
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35
docs/source/manual/file_formats/io_naming_file.rst
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@ -15,9 +15,11 @@ Under the root node ``<ports>``, naming rules can be defined line-by-line throug
.. code-block:: xml
<ports>
<port top_name="<string>" core_name="<string>" is_dummy="<bool>" direction="<string>">
<port top_name="<string>" core_name="<string>" is_dummy="<bool>" direction="<string>"/>
</ports>
.. note:: If you do not need to rename a port of an FPGA fabric, there is no need to define it explicitly in the naming rules. OpenFPGA can infer it.
Please be aware of the following restrictions:
.. note:: Please note that when naming rules should be applied to a port at its full size. For example, given a port of ``in[0:31]``, naming rules should cover all the 32 bits.
@ -26,6 +28,9 @@ Please be aware of the following restrictions:
.. warning:: Port grouping is **NOT** supported yet. For example, there are ports ``b[0:7]`` and ``c[0:7]`` from the FPGA fabric, it can **NOT** be grouped to a port ``bnc[0:15]`` at the top-level wrapper.
Syntax
``````
Detailed syntax are presented as follows.
.. option:: top_name="<string>"
@ -63,3 +68,31 @@ Detailed syntax are presented as follows.
.. code-block:: xml
direction="input"
Example
```````
Fig. :numref:`fig_fpga_core_wrapper` shows an example of a top-level wrapper with naming rules, which is built on top of an existing FPGA core fabric.
There is a dummy input port at the top-level wrapper.
.. _fig_fpga_core_wrapper:
.. figure:: figures/fpga_core_wrapper.png
:width: 100%
:alt: Illustration of a top-level wrapper on an existing FPGA core fabric
Example of a top-level wrapper: how it interfaces between SoC and an existing FPGA core fabric
The I/O naming in the Fig. :numref:`fig_fpga_core_wrapper`` can be described in the following XML:
.. code-block:: xml
<ports>
<port top_name="pclk0[0:3]" core_name="prog_clk[0:3]"/>
<port top_name="pclk1[0:3]" core_name="prog_clk[4:7]"/>
<port top_name="right_io[0:23]" core_name="pad[0:23]"/>
<port top_name="bottom_io[0:7]" core_name="pad[24:31]"/>
<port top_name="pvt_sense[0:0]" is_dummy="true" direction="input"/>
</ports>
Note that since port ``reset[0:0]`` require no name changes, it is not required to be defined in the XML.