[doc] update with example
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@ -15,9 +15,11 @@ Under the root node ``<ports>``, naming rules can be defined line-by-line throug
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.. code-block:: xml
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<ports>
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<port top_name="<string>" core_name="<string>" is_dummy="<bool>" direction="<string>">
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<port top_name="<string>" core_name="<string>" is_dummy="<bool>" direction="<string>"/>
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</ports>
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.. note:: If you do not need to rename a port of an FPGA fabric, there is no need to define it explicitly in the naming rules. OpenFPGA can infer it.
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Please be aware of the following restrictions:
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.. note:: Please note that when naming rules should be applied to a port at its full size. For example, given a port of ``in[0:31]``, naming rules should cover all the 32 bits.
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@ -26,6 +28,9 @@ Please be aware of the following restrictions:
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.. warning:: Port grouping is **NOT** supported yet. For example, there are ports ``b[0:7]`` and ``c[0:7]`` from the FPGA fabric, it can **NOT** be grouped to a port ``bnc[0:15]`` at the top-level wrapper.
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Syntax
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``````
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Detailed syntax are presented as follows.
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.. option:: top_name="<string>"
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@ -58,8 +63,36 @@ Detailed syntax are presented as follows.
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.. option:: direction="<string>"
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Direction can be ``input``|``output``|``inout``. Only applicable to dummy ports. For example,
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Direction can be ``input`` | ``output`` | ``inout``. Only applicable to dummy ports. For example,
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.. code-block:: xml
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direction="input"
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Example
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```````
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Fig. :numref:`fig_fpga_core_wrapper` shows an example of a top-level wrapper with naming rules, which is built on top of an existing FPGA core fabric.
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There is a dummy input port at the top-level wrapper.
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.. _fig_fpga_core_wrapper:
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.. figure:: figures/fpga_core_wrapper.png
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:width: 100%
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:alt: Illustration of a top-level wrapper on an existing FPGA core fabric
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Example of a top-level wrapper: how it interfaces between SoC and an existing FPGA core fabric
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The I/O naming in the Fig. :numref:`fig_fpga_core_wrapper`` can be described in the following XML:
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.. code-block:: xml
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<ports>
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<port top_name="pclk0[0:3]" core_name="prog_clk[0:3]"/>
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<port top_name="pclk1[0:3]" core_name="prog_clk[4:7]"/>
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<port top_name="right_io[0:23]" core_name="pad[0:23]"/>
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<port top_name="bottom_io[0:7]" core_name="pad[24:31]"/>
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<port top_name="pvt_sense[0:0]" is_dummy="true" direction="input"/>
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</ports>
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Note that since port ``reset[0:0]`` require no name changes, it is not required to be defined in the XML.
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