From 7945628307682a2a9a113953c61483f68d9bad39 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Sun, 7 Mar 2021 22:25:01 -0800 Subject: [PATCH] Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification --- .../quicklogic_tests/counter_5clock_test/config/task.conf | 2 +- .../tasks/quicklogic_tests/lut_adder_test/config/task.conf | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf index 3b68a8b83..92c91491e 100644 --- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml -yosys_mode = no_adder +yosys_args = -no_adder -family qlf_k4n8 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 6a5f29063..6f711649b 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -21,6 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml openfpga_vpr_circuit_format=eblif +yosys_args = -family qlf_k4n8 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -37,5 +38,5 @@ bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys # The output verilog of yosys is not synthesizable!!! # Turn off verification for now # SHOULD focus on fixing the Verilog problem and run verification at the end of the flow -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist= +#end_flow_with_test= +#vpr_fpga_verilog_formal_verification_top_netlist=