[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator
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@ -2060,7 +2060,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
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print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
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atom_ctx, place_ctx, io_location_map,
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netlist_annotation,
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bus_group,
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BusGroup(),
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std::string(),
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std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
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std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
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