riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator

This commit is contained in:
tangxifan 2022-02-18 15:41:35 -08:00
parent fe9e0ff977
commit 790715f46a
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2060,7 +2060,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module, print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
atom_ctx, place_ctx, io_location_map, atom_ctx, place_ctx, io_location_map,
netlist_annotation, netlist_annotation,
bus_group, BusGroup(),
std::string(), std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),