From 790628b22e317f7be419e673606e97bde5d00530 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 9 May 2022 16:08:31 +0800
Subject: [PATCH] [ci] add opoenfpga cell library test to ci

---
 .github/workflows/cell_lib_test.yml | 36 +++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 .github/workflows/cell_lib_test.yml

diff --git a/.github/workflows/cell_lib_test.yml b/.github/workflows/cell_lib_test.yml
new file mode 100644
index 000000000..07ac43b84
--- /dev/null
+++ b/.github/workflows/cell_lib_test.yml
@@ -0,0 +1,36 @@
+name: Cell Library Tests
+
+# Run CI on push, PR, and weekly.
+
+on:
+  push:
+  pull_request:
+  schedule:
+    - cron: "0 0 * * 0 " # weekly
+
+# Multiple job to tests
+jobs:
+  # Test the RTL compilation compatibility
+  verilog:
+    name: RTL compilation and tests
+    runs-on: ubuntu-latest
+    steps:
+      - name: Cancel previous
+        uses: styfle/cancel-workflow-action@0.9.1
+        with:
+          access_token: ${{ github.token }}
+          
+      - name: Checkout OpenFPGA repo
+        uses: actions/checkout@v2
+        with:
+          submodules: true
+
+      - name: Dump tool versions
+        run: |
+          iverilog -V
+          vvp -V
+
+      - name: Verilog compilation
+        run: |
+          cd openfpga_flow/openfpga_cell_library
+          make compile_verilog