From 78600422766f1ee90cc910261409bed477833ffc Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Fri, 3 May 2019 14:00:06 -0600 Subject: [PATCH] added before after loop breaker constraining --- vpr7_x2p/libarchfpga/include/physical_types.h | 10 ++- vpr7_x2p/libarchfpga/read_xml_arch_file.c | 29 ++++++++ .../fpga_x2p/verilog/verilog_sdc_pb_types.c | 71 +++++++------------ vpr7_x2p/vpr/SRC/pack/pb_type_graph.c | 51 +++++++++++++ 4 files changed, 114 insertions(+), 47 deletions(-) diff --git a/vpr7_x2p/libarchfpga/include/physical_types.h b/vpr7_x2p/libarchfpga/include/physical_types.h index 9e6f72085..d8951392f 100644 --- a/vpr7_x2p/libarchfpga/include/physical_types.h +++ b/vpr7_x2p/libarchfpga/include/physical_types.h @@ -319,6 +319,10 @@ struct s_interconnect { char *output_string; /* Baudouin Chauviere: SDC generation */ char *loop_breaker_string; + char *loop_breaker_delay_first_segment_min; + char *loop_breaker_delay_first_segment_max; + char *loop_breaker_delay_second_segment_min; + char *loop_breaker_delay_second_segment_max; /* END */ t_pin_to_pin_annotation *annotations; /* [0..num_annotations-1] */ @@ -545,8 +549,10 @@ struct s_pb_graph_edge { boolean is_disabled; int nb_mux; int nb_pin; - char* delay_first_segment; - char* delay_second_segment; + char* delay_first_segment_max; + char* delay_second_segment_max; + char* delay_first_segment_min; + char* delay_second_segment_min; /* END */ }; typedef struct s_pb_graph_edge t_pb_graph_edge; diff --git a/vpr7_x2p/libarchfpga/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/read_xml_arch_file.c index cc825709c..20e21dca7 100644 --- a/vpr7_x2p/libarchfpga/read_xml_arch_file.c +++ b/vpr7_x2p/libarchfpga/read_xml_arch_file.c @@ -1411,6 +1411,35 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) { mode->interconnect[i].loop_breaker_string= my_strdup(Prop); } ezxml_set_attr(Cur, "loop_breaker", NULL); + + Cur2 = FindFirstElement(Cur, "delay_first_segment", FALSE); + if (NULL != Cur2) { + Prop = FindProperty(Cur2, "min", FALSE); + if (NULL != Prop) { + mode->interconnect[i].loop_breaker_delay_first_segment_min = my_strdup(Prop); + ezxml_set_attr(Cur2, "min", NULL); + } + Prop = FindProperty(Cur2, "max", FALSE); + if (NULL != Prop) { + mode->interconnect[i].loop_breaker_delay_first_segment_max = my_strdup(Prop); + ezxml_set_attr(Cur2, "max", NULL); + } + FreeNode(Cur2); + } + Cur2 = FindFirstElement(Cur, "delay_second_segment", FALSE); + if (NULL != Cur2) { + Prop = FindProperty(Cur2, "min", FALSE); + if (NULL != Prop) { + mode->interconnect[i].loop_breaker_delay_second_segment_min = my_strdup(Prop); + ezxml_set_attr(Cur2, "min", NULL); + } + Prop = FindProperty(Cur2, "max", FALSE); + if (NULL != Prop) { + mode->interconnect[i].loop_breaker_delay_second_segment_max = my_strdup(Prop); + ezxml_set_attr(Cur2, "max", NULL); + } + FreeNode(Cur2); + } /* END */ /* Process delay and capacitance annotations */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c index 96768ad55..dd153b5c9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc_pb_types.c @@ -55,51 +55,24 @@ void sdc_dump_annotation(char* from_path, // includes the cell FILE* fp, t_pb_graph_edge* cur_edge){ - //char* min_value = NULL; - t_interconnect* cur_interconnect; - float max_value = NULL; + float min_value = 0; + float max_value = 0; int i,j; // Find in the annotations the min and max - - cur_interconnect = cur_edge->interconnect; - for (i=0; i < cur_interconnect->num_annotations; i++) { - if (E_ANNOT_PIN_TO_PIN_DELAY == cur_interconnect->annotations[i].type) { - for (j=0; j < cur_interconnect->annotations[i].num_value_prop_pairs; j++) { - /* if (E_ANNOT_PIN_TO_PIN_DELAY_MIN == interconnect->annotations[i].prop[j]) { - min_value = cur_edge->delay_min; - min_value = max_value*pow(10,9); - }*/ - if(E_ANNOT_PIN_TO_PIN_DELAY_MAX == cur_interconnect->annotations[i].prop[j]) { - max_value = cur_edge->delay_max; - max_value = max_value*pow(10,9); /* converts sec in ns */ - } - } - } + if (0 != cur_edge->delay_min) { + min_value = cur_edge->delay_min; + min_value = min_value*pow(10,9); + fprintf (fp, "set_min_delay -combinational_from_to -from %s -to %s ", from_path, to_path); + fprintf (fp,"%f\n", min_value); } - - - // Dump the annotation - // If no annotation was found, dump 0 - - /* fprintf (fp, "set_min_delay -from %s -to %s ", from_path,to_path); - if (NULL != min_value) { - fprintf(fp, "%s\n", min_value); - } else { - fprintf(fp, "0\n"); - } */ - - /*fprintf (fp, "set_max_delay -from %s -to %s ", from_path, to_path); - if (max_value != NULL){ - fprintf (fp,"%s\n",max_value); - } else { - fprintf (fp,"0\n"); - }*/ - if (max_value != NULL){ - fprintf (fp, "set_max_delay -combinational_from_to -from %s -to %s ", from_path, to_path); - fprintf (fp,"%f\n", max_value); - } -return; + if (0 != cur_edge->delay_max) { + max_value = cur_edge->delay_max; + max_value = max_value*pow(10,9); + fprintf (fp, "set_max_delay -combinational_from_to -from %s -to %s ", from_path, to_path); + fprintf (fp,"%f\n", max_value); + } + return; } @@ -278,14 +251,22 @@ void dump_sdc_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, sprintf(set_disable_path, "%s/%s_%d_", input_buffer_path, input_buffer_name, des_pb_graph_pin->input_edges[iedge]->nb_pin); - if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment) { + if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min) { + fprintf (fp, "set_min_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in, + des_pb_graph_pin->input_edges[iedge]->delay_first_segment_min); + } + if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max) { fprintf (fp, "set_max_delay -from %s -to %s/%s %s \n", from_path, set_disable_path, input_buffer_in, - to_path, des_pb_graph_pin->input_edges[iedge]->delay_first_segment); + des_pb_graph_pin->input_edges[iedge]->delay_first_segment_max); } fprintf (fp, "set_disable_timing -from %s -to %s %s \n", input_buffer_in, input_buffer_out, set_disable_path); - if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment) { + if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min) { + fprintf (fp, "set_min_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out, + to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_min); + } + if (NULL != des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max) { fprintf (fp, "set_max_delay -from %s/%s -to %s %s \n", set_disable_path, input_buffer_out, - to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment); + to_path, des_pb_graph_pin->input_edges[iedge]->delay_second_segment_max); } my_free(input_buffer_path); my_free(set_disable_path); diff --git a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c index 4b59d62c2..f0967f2da 100755 --- a/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c +++ b/vpr7_x2p/vpr/SRC/pack/pb_type_graph.c @@ -2070,6 +2070,23 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, i_num_output_edges ++) { if (cur_interc == cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + + if (NULL != cur_interc->loop_breaker_delay_first_segment_min) { + cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min + = cur_interc->loop_breaker_delay_first_segment_min; + } + if (NULL != cur_interc->loop_breaker_delay_first_segment_max) { + cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max + = cur_interc->loop_breaker_delay_first_segment_max; + } + if (NULL != cur_interc->loop_breaker_delay_second_segment_min) { + cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min + = cur_interc->loop_breaker_delay_second_segment_min; + } + if (NULL != cur_interc->loop_breaker_delay_second_segment_max) { + cur_node[i_index_cur_node]->input_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max + = cur_interc->loop_breaker_delay_second_segment_max; + } } } break; @@ -2079,6 +2096,23 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, i_num_output_edges ++) { if (cur_interc == cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + + if (NULL != cur_interc->loop_breaker_delay_first_segment_min) { + cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min + = cur_interc->loop_breaker_delay_first_segment_min; + } + if (NULL != cur_interc->loop_breaker_delay_first_segment_max) { + cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max + = cur_interc->loop_breaker_delay_first_segment_max; + } + if (NULL != cur_interc->loop_breaker_delay_second_segment_min) { + cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min + = cur_interc->loop_breaker_delay_second_segment_min; + } + if (NULL != cur_interc->loop_breaker_delay_second_segment_max) { + cur_node[i_index_cur_node]->output_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max + = cur_interc->loop_breaker_delay_second_segment_max; + } } } break; @@ -2088,6 +2122,23 @@ static void map_loop_breaker_onto_edges(char* loop_breaker_string, int line_num, i_num_output_edges ++) { if (cur_interc == cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->interconnect) { cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->is_disabled = TRUE; + + if (NULL != cur_interc->loop_breaker_delay_first_segment_min) { + cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_min + = cur_interc->loop_breaker_delay_first_segment_min; + } + if (NULL != cur_interc->loop_breaker_delay_first_segment_max) { + cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_first_segment_max + = cur_interc->loop_breaker_delay_first_segment_max; + } + if (NULL != cur_interc->loop_breaker_delay_second_segment_min) { + cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_min + = cur_interc->loop_breaker_delay_second_segment_min; + } + if (NULL != cur_interc->loop_breaker_delay_second_segment_max) { + cur_node[i_index_cur_node]->clock_pins[cur_port_index][cur_pin_index].output_edges[i_num_output_edges]->delay_second_segment_max + = cur_interc->loop_breaker_delay_second_segment_max; + } } } break;