Added execution time logs in flow script
This commit is contained in:
Ganesh Gore
parent
30cbe38d3d
commit
77e2a7bca3
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@ -2,6 +2,7 @@ import os
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import sys
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import shutil
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import time
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from datetime import timedelta
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import shlex
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import glob
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import argparse
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@ -13,6 +14,9 @@ import threading
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from string import Template
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import re
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import xml.etree.ElementTree as ET
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from importlib import util
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if util.find_spec("humanize"):
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import humanize
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Initialise general paths for the script
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@ -188,13 +192,14 @@ RegParse.add_argument("--end_flow_with_test", action="store_true",
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Global varaibles declaration
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Varible to store logger instance
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logger = None
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# arguments are parsed at the end of the script depending upon whether script
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# is called externally or as a standalone
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args = None
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# Setting up print and logging system
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logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s - %(message)s')
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logger = logging.getLogger('OpenFPGA_Flow_Logs')
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# variable to store script_configuration and cad tool paths
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config, cad_tools = None, None
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ExecTime = {}
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Main program starts here
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@ -211,9 +216,9 @@ def main():
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logger.info('Running "yosys_vpr" Flow')
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run_yosys_with_abc()
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run_rewrite_verilog()
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if args.power:
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run_ace2()
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run_pro_blif_3arg()
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if args.power:
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run_ace2()
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run_pro_blif_3arg()
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if (args.fpga_flow == "vpr_blif"):
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collect_files_for_vpr()
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# if (args.fpga_flow == "vtr"):
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@ -224,6 +229,20 @@ def main():
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run_vpr()
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if args.end_flow_with_test:
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run_netlists_verification()
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ExecTime["End"] = time.time()
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def timestr(x): return humanize.naturaldelta(timedelta(seconds=x)) \
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if "humanize" in sys.modules else str(int(x)) + " Sec "
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TimeInfo = ("Openfpga_flow completed, " +
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"Total Time Taken %s " %
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timestr(ExecTime["End"]-ExecTime["Start"]) +
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"VPR Time %s " %
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timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"]))
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TimeInfo += ("Verification Time %s " %
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timestr(ExecTime["VerificationEnd"] -
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ExecTime["VerificationStart"])
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if args.end_flow_with_test else "")
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logger.info(TimeInfo)
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exit()
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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@ -270,7 +289,7 @@ def validate_command_line_arguments():
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# Check if flow supported
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if not args.fpga_flow in config.get("FLOW_SCRIPT_CONFIG", "valid_flows"):
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clean_up_and_exit("%s Flow not supported"%args.fpga_flow)
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clean_up_and_exit("%s Flow not supported" % args.fpga_flow)
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# Check if argument list is consistant
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for eacharg, dependent in config.items("CMD_ARGUMENT_DEPENDANCY"):
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@ -278,8 +297,8 @@ def validate_command_line_arguments():
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dependent = dependent.split(",")
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for eachdep in dependent:
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if not any([getattr(args, i, 0) for i in eachdep.split("|")]):
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clean_up_and_exit("'%s' argument depends on (%s) argumets"%
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(eacharg, ", ".join(dependent).replace("|", " or ")))
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clean_up_and_exit("'%s' argument depends on (%s) argumets" %
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(eacharg, ", ".join(dependent).replace("|", " or ")))
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# Filter provided architecrue files
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args.arch_file = os.path.abspath(args.arch_file)
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@ -292,7 +311,7 @@ def validate_command_line_arguments():
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if os.path.isdir(args.benchmark_files[index]):
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logger.warning("Skipping directory in bench %s" % everyinput)
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logger.warning("Directory is not support in benchmark list" +
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"use wildcard pattern to add files")
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"use wildcard pattern to add files")
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continue
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for everyfile in glob.glob(args.benchmark_files[index]):
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if not os.path.isfile(everyfile):
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@ -515,15 +534,25 @@ def run_pro_blif_3arg():
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logger.info("blif_3args output is written in file %s" % filename)
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def collect_files_for_vpr():
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if len(args.benchmark_files) > 1:
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logger.error("Expecting Single Benchmark BLif file.")
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shutil.copy(args.benchmark_files[0], args.top_module+".blif")
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shutil.copy(args.activity_file, args.top_module+"_ace_out.act")
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shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
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def run_vpr():
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ExecTime["VPRStart"] = time.time()
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if not args.fix_route_chan_width:
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# Run Standard VPR Flow
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min_channel_width = run_standard_vpr(
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args.top_module+".blif",
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-1,
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args.top_module+"_min_chan_width_vpr.txt")
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logger.info("Standard VPR flow routed with minimum %d Channels" %
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min_channel_width)
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# Run Standard VPR Flow
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min_channel_width = run_standard_vpr(
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args.top_module+".blif",
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-1,
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args.top_module+"_min_chan_width_vpr.txt")
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logger.info("Standard VPR flow routed with minimum %d Channels" %
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min_channel_width)
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# Minimum routing channel width
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if (args.min_route_chan_width):
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@ -536,8 +565,8 @@ def run_vpr():
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while(1):
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res = run_standard_vpr(args.top_module+".blif",
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int(min_channel_width),
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args.top_module+"_reroute_vpr.txt",
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route_only=True)
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args.top_module+"_reroute_vpr.txt",
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route_only=True)
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if res:
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logger.info("Routing with channel width=%d successful" %
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@ -568,6 +597,7 @@ def run_vpr():
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extract_vpr_stats(logfile=args.top_module+".power",
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r_filename="vpr_power_stat",
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parse_section="power")
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ExecTime["VPREnd"] = time.time()
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def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
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@ -690,6 +720,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
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chan_width = None
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try:
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logger.debug("Running VPR : " + " ".join(command))
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with open(logfile, 'w+') as output:
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output.write(" ".join(command)+"\n")
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process = subprocess.run(command,
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@ -737,8 +768,8 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
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extract_val = str(match.group(1))
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elif filt_function.strip() == "scientific":
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try:
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mult = {"m":1E-3, "u":1E-6, "n":1E-9,
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"K":1E-3, "M":1E-6, "G":1E-9,}.get(match.group(2)[0], 1)
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mult = {"m": 1E-3, "u": 1E-6, "n": 1E-9,
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"K": 1E-3, "M": 1E-6, "G": 1E-9, }.get(match.group(2)[0], 1)
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except:
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mult = 1
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extract_val = float(match.group(1))*mult
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@ -746,7 +777,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
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extract_val = match.group(1)
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except:
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logger.exception("Filter failed")
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extract_val= "Filter Failed"
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extract_val = "Filter Failed"
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resultDict[name] = extract_val
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dummyparser = ConfigParser()
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@ -755,7 +786,7 @@ def extract_vpr_stats(logfile, r_filename="vpr_stat", parse_section="vpr"):
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with open(r_filename+'.result', 'w') as configfile:
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dummyparser.write(configfile)
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logger.info("%s result extracted in file %s" %
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(parse_section,r_filename+'.result'))
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(parse_section, r_filename+'.result'))
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def run_rewrite_verilog():
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@ -776,13 +807,15 @@ def run_rewrite_verilog():
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if process.returncode:
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logger.info("Rewrite veri yosys run failed with returncode %d",
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process.returncode)
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except:
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except Exception as e:
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logger.exception("Failed to run VPR")
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print(e.output)
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clean_up_and_exit("")
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logger.info("Yosys output is written in file yosys_rewrite_veri_output.txt")
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def run_netlists_verification():
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ExecTime["VerificationStart"] = time.time()
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compiled_file = "compiled_"+args.top_module
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# include_netlists = args.top_module+"_include_netlists.v"
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tb_top_formal = args.top_module+"_top_formal_verification_random_tb"
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@ -806,6 +839,7 @@ def run_netlists_verification():
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logger.info("VVP Simulation Successful")
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else:
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logger.info(str(output).split("\n")[-1])
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ExecTime["VerificationEnd"] = time.time()
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def run_command(taskname, logfile, command, exit_if_fail=True):
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@ -840,11 +874,6 @@ def process_failed_vpr_run(vpr_output):
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if __name__ == "__main__":
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# Setting up print and logging system
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logging.basicConfig(level=logging.DEBUG, stream=sys.stdout,
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format='%(levelname)s - %(message)s')
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logger = logging.getLogger('OpenFPGA_Flow_Logs')
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# Parse commandline argument
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ExecTime["Start"] = time.time()
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args = parser.parse_args()
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main()
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