Added execution time logs in flow script

openfpga_flow/scripts/run_fpga_flow.py

@@ -2,6 +2,7 @@ import os
 import sys
 import shutil
 import time
+from datetime import timedelta
 import shlex
 import glob
 import argparse
@@ -13,6 +14,9 @@ import threading
 from string import Template
 import re
 import xml.etree.ElementTree as ET
+from importlib import util
+if util.find_spec("humanize"):
+    import humanize
 
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Initialise general paths for the script
@@ -188,13 +192,14 @@ RegParse.add_argument("--end_flow_with_test", action="store_true",
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Global varaibles declaration
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Varible to store logger instance
-logger = None
-# arguments are parsed at the end of the script depending upon whether script
-# is called externally or as a standalone
-args = None
+# Setting up print and logging system
+logging.basicConfig(level=logging.INFO, stream=sys.stdout,
+                    format='%(levelname)s - %(message)s')
+logger = logging.getLogger('OpenFPGA_Flow_Logs')
+
 # variable to store script_configuration and cad tool paths
 config, cad_tools = None, None
+ExecTime = {}
 
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Main program starts here
@@ -224,6 +229,20 @@ def main():
     run_vpr()
     if args.end_flow_with_test:
         run_netlists_verification()
+
+    ExecTime["End"] = time.time()
+    def timestr(x): return humanize.naturaldelta(timedelta(seconds=x)) \
+        if "humanize" in sys.modules else str(int(x)) + " Sec "
+    TimeInfo = ("Openfpga_flow completed, " +
+                "Total Time Taken %s " %
+                timestr(ExecTime["End"]-ExecTime["Start"]) +
+                "VPR Time %s " %
+                timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"]))
+    TimeInfo += ("Verification Time %s " %
+                 timestr(ExecTime["VerificationEnd"] -
+                         ExecTime["VerificationStart"])
+                 if args.end_flow_with_test else "")
+    logger.info(TimeInfo)
     exit()
 
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
@@ -515,7 +534,17 @@ def run_pro_blif_3arg():
     logger.info("blif_3args output is written in file %s" % filename)
 
 
+def collect_files_for_vpr():
+    if len(args.benchmark_files) > 1:
+        logger.error("Expecting Single Benchmark BLif file.")
+    shutil.copy(args.benchmark_files[0], args.top_module+".blif")
+    shutil.copy(args.activity_file, args.top_module+"_ace_out.act")
+    shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v")
+
+
 def run_vpr():
+    ExecTime["VPRStart"] = time.time()
+
     if not args.fix_route_chan_width:
         # Run Standard VPR Flow
         min_channel_width = run_standard_vpr(
@@ -568,6 +597,7 @@ def run_vpr():
         extract_vpr_stats(logfile=args.top_module+".power",
                           r_filename="vpr_power_stat",
                           parse_section="power")
+    ExecTime["VPREnd"] = time.time()
 
 
 def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
@@ -690,6 +720,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
 
     chan_width = None
     try:
+        logger.debug("Running VPR : " + " ".join(command))
         with open(logfile, 'w+') as output:
             output.write(" ".join(command)+"\n")
             process = subprocess.run(command,
@@ -776,13 +807,15 @@ def run_rewrite_verilog():
             if process.returncode:
                 logger.info("Rewrite veri yosys run failed with returncode %d",
                             process.returncode)
-    except:
+    except Exception as e:
         logger.exception("Failed to run VPR")
+        print(e.output)
         clean_up_and_exit("")
     logger.info("Yosys output is written in file yosys_rewrite_veri_output.txt")
 
 
 def run_netlists_verification():
+    ExecTime["VerificationStart"] = time.time()
     compiled_file = "compiled_"+args.top_module
     # include_netlists = args.top_module+"_include_netlists.v"
     tb_top_formal = args.top_module+"_top_formal_verification_random_tb"
@@ -806,6 +839,7 @@ def run_netlists_verification():
         logger.info("VVP Simulation Successful")
     else:
         logger.info(str(output).split("\n")[-1])
+    ExecTime["VerificationEnd"] = time.time()
 
 
 def run_command(taskname, logfile, command, exit_if_fail=True):
@@ -840,11 +874,6 @@ def process_failed_vpr_run(vpr_output):
 
 
 if __name__ == "__main__":
-    # Setting up print and logging system
-    logging.basicConfig(level=logging.DEBUG, stream=sys.stdout,
-                        format='%(levelname)s - %(message)s')
-    logger = logging.getLogger('OpenFPGA_Flow_Logs')
-
-    # Parse commandline argument
+    ExecTime["Start"] = time.time()
     args = parser.parse_args()
     main()