From ee392f1b46a83bee0d21f6b68a8255d301c1bdcd Mon Sep 17 00:00:00 2001 From: ubuntu Date: Tue, 21 Nov 2023 21:47:03 -0800 Subject: [PATCH 01/26] add ignore_net to repackdesign constraint --- .../src/base/repack_design_constraints.cpp | 9 ++++ .../src/base/repack_design_constraints.h | 6 +++ .../io/read_xml_repack_design_constraints.cpp | 14 +++-- openfpga/src/repack/repack.cpp | 11 ++-- openfpga/src/repack/repack_option.cpp | 54 +++++++++++++++++++ openfpga/src/repack/repack_option.h | 3 ++ 6 files changed, 89 insertions(+), 8 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index 220a2d41c..b72e7fe82 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -54,6 +54,11 @@ std::string RepackDesignConstraints::net( return repack_design_constraint_nets_[repack_design_constraint_id]; } +std::map> +RepackDesignConstraints::ignore_net_pin_map() const { + return ignore_net_pin_map_; +} + std::string RepackDesignConstraints::find_constrained_pin_net( const std::string& pb_type, const openfpga::BasicPort& pin) const { std::string constrained_net_name; @@ -138,6 +143,10 @@ void RepackDesignConstraints::set_net( repack_design_constraint_nets_[repack_design_constraint_id] = net; } +void RepackDesignConstraints::set_ignore_net_pin_map_( + const std::string& net_name, const std::string pin_ctx) { + ignore_net_pin_map_[net_name].push_back(pin_ctx); +} /************************************************************************ * Internal invalidators/validators ***********************************************************************/ diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 31db9562d..2d7659642 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -69,6 +69,7 @@ class RepackDesignConstraints { std::string net( const RepackDesignConstraintId& repack_design_constraint_id) const; + std::map> ignore_net_pin_map() const; /* Find a constrained net */ std::string find_constrained_pin_net(const std::string& pb_type, const openfpga::BasicPort& pin) const; @@ -98,6 +99,9 @@ class RepackDesignConstraints { void set_net(const RepackDesignConstraintId& repack_design_constraint_id, const std::string& net); + void set_ignore_net_pin_map_(const std::string& net_name, + const std::string pin_ctx); + public: /* Public invalidators/validators */ bool valid_design_constraint_id( const RepackDesignConstraintId& repack_design_constraint_id) const; @@ -135,6 +139,8 @@ class RepackDesignConstraints { /* Nets to constraint */ vtr::vector repack_design_constraint_nets_; + + std::map> ignore_net_pin_map_; }; #endif diff --git a/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp b/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp index 008aac3ca..f3975d8cd 100644 --- a/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp +++ b/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp @@ -80,11 +80,17 @@ RepackDesignConstraints read_xml_repack_design_constraints( for (pugi::xml_node xml_design_constraint : xml_root.children()) { /* Error out if the XML child has an invalid name! */ - if (xml_design_constraint.name() != std::string("pin_constraint")) { - bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint"}); + if (xml_design_constraint.name() == std::string("pin_constraint")) { + read_xml_pin_constraint(xml_design_constraint, loc_data, + repack_design_constraints); + } else if (xml_design_constraint.name() == std::string("ignore_net")) { + repack_design_constraints.set_ignore_net_pin_map_( + get_attribute(xml_design_constraint, "name", loc_data).as_string(), + get_attribute(xml_design_constraint, "pin", loc_data).as_string()); + } else { + bad_tag(xml_design_constraint, loc_data, xml_root, + {"pin_constraint", "ignore_net"}); } - read_xml_pin_constraint(xml_design_constraint, loc_data, - repack_design_constraints); } } catch (pugiutil::XmlError& e) { archfpga_throw(design_constraint_fname, e.line(), "%s", e.what()); diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index f80a42a41..23955ba63 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -575,10 +575,13 @@ static void add_lb_router_nets( /* Only for global net which should be ignored, cache the sink nodes */ BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); - if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id)) && - (clustering_ctx.clb_nlist.net_is_global(cluster_net_id)) && - (options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), - curr_pin))) { +if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id) && + clustering_ctx.clb_nlist.net_is_global(cluster_net_id) && + options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), + curr_pin)) || + (options.net_is_specified_to_be_ignored( + atom_ctx.nlist.net_name(pb_pin_mapped_nets[source_pb_pin]), + std::string(lb_type->pb_type->name), curr_pin))){ /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index b3a06f60f..fdff5e5c0 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -46,6 +46,60 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name, return false; } +bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, + std::string pb_type_name, + const BasicPort& port) const { + if (cluster_net_name == "rst_n") int tt = 0; + auto result = design_constraints_.ignore_net_pin_map().find(cluster_net_name); + if (result == design_constraints_.ignore_net_pin_map().end()) { + /* Not found, return false */ + return false; + } else { + int num_parse_errors_temp = 0; + /* Split the content using a tokenizer */ + auto pin_ctx_to_parse = + design_constraints_.ignore_net_pin_map()[cluster_net_name]; + for (auto pin_ctx_to_parse_iter : pin_ctx_to_parse) { + StringToken tokenizer(pin_ctx_to_parse_iter); + std::vector tokens = tokenizer.split(','); + /* Parse each token */ + for (std::string token : tokens) { + /* Extract the pb_type name and port name */ + StringToken pin_tokenizer(token); + std::vector pin_info = pin_tokenizer.split('.'); + /* Expect two contents, otherwise error out */ + if (pin_info.size() != 2) { + std::string err_msg = + std::string("Invalid content '") + token + + std::string("' to skip, expect .\n"); + VTR_LOG_ERROR(err_msg.c_str()); + num_parse_errors_temp++; + continue; + } + std::string curr_pb_type_name = pin_info[0]; + PortParser port_parser(pin_info[1]); + BasicPort curr_port = port_parser.port(); + if (!curr_port.is_valid()) { + std::string err_msg = + std::string("Invalid pin definition '") + token + + std::string("', expect .[int:int]\n"); + VTR_LOG_ERROR(err_msg.c_str()); + num_parse_errors_temp++; + continue; + } + // if (curr_pb_type_name == pb_type_name && curr_port == port) { + // return true; + // } + if (curr_port.mergeable(port) && curr_port.contained(port) && + curr_pb_type_name == pb_type_name) { + return true; + } + } + } + } + return false; +} + bool RepackOption::verbose_output() const { return verbose_output_; } /****************************************************************************** diff --git a/openfpga/src/repack/repack_option.h b/openfpga/src/repack/repack_option.h index 24f46633d..f5ff09bef 100644 --- a/openfpga/src/repack/repack_option.h +++ b/openfpga/src/repack/repack_option.h @@ -25,6 +25,9 @@ class RepackOption { /* Identify if a pin should ignore all the global nets */ bool is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const; + bool net_is_specified_to_be_ignored( + std::string cluster_net_name, std::string pb_type_name, + const BasicPort& port) const; bool verbose_output() const; public: /* Public mutators */ From 8f9161b438388dca69888656cb5e2754242ee2b2 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Tue, 21 Nov 2023 22:28:37 -0800 Subject: [PATCH 02/26] format the code --- openfpga/src/repack/repack_option.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index fdff5e5c0..b143d6359 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -49,7 +49,6 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name, bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, std::string pb_type_name, const BasicPort& port) const { - if (cluster_net_name == "rst_n") int tt = 0; auto result = design_constraints_.ignore_net_pin_map().find(cluster_net_name); if (result == design_constraints_.ignore_net_pin_map().end()) { /* Not found, return false */ @@ -87,9 +86,6 @@ bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, num_parse_errors_temp++; continue; } - // if (curr_pb_type_name == pb_type_name && curr_port == port) { - // return true; - // } if (curr_port.mergeable(port) && curr_port.contained(port) && curr_pb_type_name == pb_type_name) { return true; From 93d5b850f073f2e4ee99112072db0bf43488b308 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Wed, 22 Nov 2023 00:04:51 -0800 Subject: [PATCH 03/26] reset the error flag in each parsing iteration --- openfpga/src/repack/repack_option.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index b143d6359..7603b12e7 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -54,11 +54,11 @@ bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, /* Not found, return false */ return false; } else { - int num_parse_errors_temp = 0; /* Split the content using a tokenizer */ auto pin_ctx_to_parse = design_constraints_.ignore_net_pin_map()[cluster_net_name]; for (auto pin_ctx_to_parse_iter : pin_ctx_to_parse) { + int num_parse_errors_temp = 0; StringToken tokenizer(pin_ctx_to_parse_iter); std::vector tokens = tokenizer.split(','); /* Parse each token */ From e3682ac9556dc2d2d982e87c1e346f062e64f347 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Wed, 22 Nov 2023 01:15:55 -0800 Subject: [PATCH 04/26] reformate the code --- openfpga/src/repack/repack.cpp | 4 ++-- openfpga/src/repack/repack_option.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 23955ba63..35f45d7a1 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -575,13 +575,13 @@ static void add_lb_router_nets( /* Only for global net which should be ignored, cache the sink nodes */ BasicPort curr_pin(std::string(source_pb_pin->port->name), source_pb_pin->pin_number, source_pb_pin->pin_number); -if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id) && + if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id) && clustering_ctx.clb_nlist.net_is_global(cluster_net_id) && options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), curr_pin)) || (options.net_is_specified_to_be_ignored( atom_ctx.nlist.net_name(pb_pin_mapped_nets[source_pb_pin]), - std::string(lb_type->pb_type->name), curr_pin))){ + std::string(lb_type->pb_type->name), curr_pin))) { /* Find the net mapped to this pin in clustering results*/ AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin]; diff --git a/openfpga/src/repack/repack_option.h b/openfpga/src/repack/repack_option.h index f5ff09bef..76868a83e 100644 --- a/openfpga/src/repack/repack_option.h +++ b/openfpga/src/repack/repack_option.h @@ -25,9 +25,9 @@ class RepackOption { /* Identify if a pin should ignore all the global nets */ bool is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const; - bool net_is_specified_to_be_ignored( - std::string cluster_net_name, std::string pb_type_name, - const BasicPort& port) const; + bool net_is_specified_to_be_ignored(std::string cluster_net_name, + std::string pb_type_name, + const BasicPort& port) const; bool verbose_output() const; public: /* Public mutators */ From d4720d9884f5404fa344cc2232c06020d4f5f2a4 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Tue, 28 Nov 2023 02:04:42 -0800 Subject: [PATCH 05/26] minor change --- libs/libpcf/src/base/repack_design_constraints.cpp | 12 +++++++++--- libs/libpcf/src/base/repack_design_constraints.h | 2 +- openfpga/src/repack/repack_option.cpp | 7 +++---- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index b72e7fe82..68f926042 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -54,9 +54,15 @@ std::string RepackDesignConstraints::net( return repack_design_constraint_nets_[repack_design_constraint_id]; } -std::map> -RepackDesignConstraints::ignore_net_pin_map() const { - return ignore_net_pin_map_; +std::vector RepackDesignConstraints::ignore_net_on_pin( + const std::string& net_name) const { + std::map>::const_iterator it = + ignore_net_pin_map_.find(net_name); + if (it != ignore_net_pin_map_.end()) { + return it->second; + } else { + return std::vector(); + } } std::string RepackDesignConstraints::find_constrained_pin_net( diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 2d7659642..c0de2bc85 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -69,7 +69,7 @@ class RepackDesignConstraints { std::string net( const RepackDesignConstraintId& repack_design_constraint_id) const; - std::map> ignore_net_pin_map() const; + std::vector ignore_net_on_pin(const std::string& net_name) const; /* Find a constrained net */ std::string find_constrained_pin_net(const std::string& pb_type, const openfpga::BasicPort& pin) const; diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index 7603b12e7..51581f072 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -49,14 +49,13 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name, bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, std::string pb_type_name, const BasicPort& port) const { - auto result = design_constraints_.ignore_net_pin_map().find(cluster_net_name); - if (result == design_constraints_.ignore_net_pin_map().end()) { + auto pin_ctx_to_parse = + design_constraints_.ignore_net_on_pin(cluster_net_name); + if (pin_ctx_to_parse.empty()) { /* Not found, return false */ return false; } else { /* Split the content using a tokenizer */ - auto pin_ctx_to_parse = - design_constraints_.ignore_net_pin_map()[cluster_net_name]; for (auto pin_ctx_to_parse_iter : pin_ctx_to_parse) { int num_parse_errors_temp = 0; StringToken tokenizer(pin_ctx_to_parse_iter); From d28f024b61b32f6620cbde66a0a253a547fa455a Mon Sep 17 00:00:00 2001 From: ubuntu Date: Tue, 28 Nov 2023 02:04:42 -0800 Subject: [PATCH 06/26] minor change --- libs/libpcf/src/base/repack_design_constraints.cpp | 12 +++++++++--- libs/libpcf/src/base/repack_design_constraints.h | 2 +- openfpga/src/repack/repack_option.cpp | 7 +++---- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index b72e7fe82..68f926042 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -54,9 +54,15 @@ std::string RepackDesignConstraints::net( return repack_design_constraint_nets_[repack_design_constraint_id]; } -std::map> -RepackDesignConstraints::ignore_net_pin_map() const { - return ignore_net_pin_map_; +std::vector RepackDesignConstraints::ignore_net_on_pin( + const std::string& net_name) const { + std::map>::const_iterator it = + ignore_net_pin_map_.find(net_name); + if (it != ignore_net_pin_map_.end()) { + return it->second; + } else { + return std::vector(); + } } std::string RepackDesignConstraints::find_constrained_pin_net( diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 2d7659642..c0de2bc85 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -69,7 +69,7 @@ class RepackDesignConstraints { std::string net( const RepackDesignConstraintId& repack_design_constraint_id) const; - std::map> ignore_net_pin_map() const; + std::vector ignore_net_on_pin(const std::string& net_name) const; /* Find a constrained net */ std::string find_constrained_pin_net(const std::string& pb_type, const openfpga::BasicPort& pin) const; diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index 7603b12e7..51581f072 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -49,14 +49,13 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name, bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, std::string pb_type_name, const BasicPort& port) const { - auto result = design_constraints_.ignore_net_pin_map().find(cluster_net_name); - if (result == design_constraints_.ignore_net_pin_map().end()) { + auto pin_ctx_to_parse = + design_constraints_.ignore_net_on_pin(cluster_net_name); + if (pin_ctx_to_parse.empty()) { /* Not found, return false */ return false; } else { /* Split the content using a tokenizer */ - auto pin_ctx_to_parse = - design_constraints_.ignore_net_pin_map()[cluster_net_name]; for (auto pin_ctx_to_parse_iter : pin_ctx_to_parse) { int num_parse_errors_temp = 0; StringToken tokenizer(pin_ctx_to_parse_iter); From 030f9d883762da2a95c4669e5721bea72b0116f7 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Wed, 29 Nov 2023 02:12:07 -0800 Subject: [PATCH 07/26] changes according to code review --- .../src/base/repack_design_constraints.cpp | 31 ++++++++++++++++--- .../src/base/repack_design_constraints.h | 8 ++--- 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index 68f926042..8a3fa7f76 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -2,6 +2,8 @@ #include +#include "openfpga_port_parser.h" +#include "openfpga_tokenizer.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -54,14 +56,14 @@ std::string RepackDesignConstraints::net( return repack_design_constraint_nets_[repack_design_constraint_id]; } -std::vector RepackDesignConstraints::ignore_net_on_pin( +std::set RepackDesignConstraints::ignore_net_on_pin( const std::string& net_name) const { - std::map>::const_iterator it = + std::map>::const_iterator it = ignore_net_pin_map_.find(net_name); if (it != ignore_net_pin_map_.end()) { return it->second; } else { - return std::vector(); + return std::set(); } } @@ -151,7 +153,28 @@ void RepackDesignConstraints::set_net( void RepackDesignConstraints::set_ignore_net_pin_map_( const std::string& net_name, const std::string pin_ctx) { - ignore_net_pin_map_[net_name].push_back(pin_ctx); + /* Extract the pb_type name and port name */ + openfpga::StringToken pin_tokenizer(pin_ctx); + std::vector pin_info = pin_tokenizer.split('.'); + /* Expect two contents, otherwise error out */ + if (pin_info.size() != 2) { + std::string err_msg = + std::string("Invalid content '") + pin_ctx + + std::string("' to skip, expect .\n"); + VTR_LOG_ERROR(err_msg.c_str()); + return; + } + std::string pb_type_name = pin_info[0]; + openfpga::PortParser port_parser(pin_info[1]); + openfpga::BasicPort curr_port = port_parser.port(); + if (!curr_port.is_valid()) { + std::string err_msg = + std::string("Invalid pin definition '") + pin_ctx + + std::string("', expect .[int:int]\n"); + VTR_LOG_ERROR(err_msg.c_str()); + return; + } + ignore_net_pin_map_[net_name].insert(pin_ctx); } /************************************************************************ * Internal invalidators/validators diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index c0de2bc85..6401b5f1b 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -7,7 +7,7 @@ #include #include #include - +#include /* Headers from vtrutil library */ #include "vtr_geometry.h" #include "vtr_vector.h" @@ -69,7 +69,7 @@ class RepackDesignConstraints { std::string net( const RepackDesignConstraintId& repack_design_constraint_id) const; - std::vector ignore_net_on_pin(const std::string& net_name) const; + std::set ignore_net_on_pin(const std::string& net_name) const; /* Find a constrained net */ std::string find_constrained_pin_net(const std::string& pb_type, const openfpga::BasicPort& pin) const; @@ -139,8 +139,8 @@ class RepackDesignConstraints { /* Nets to constraint */ vtr::vector repack_design_constraint_nets_; - - std::map> ignore_net_pin_map_; + + std::map> ignore_net_pin_map_; // std::set }; #endif From 2511b79bd6f7c0d560dbafcc8931aa210a39ead5 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Wed, 29 Nov 2023 02:27:53 -0800 Subject: [PATCH 08/26] format the code --- libs/libpcf/src/base/repack_design_constraints.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 6401b5f1b..0dc058628 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -6,8 +6,8 @@ *******************************************************************/ #include #include -#include #include +#include /* Headers from vtrutil library */ #include "vtr_geometry.h" #include "vtr_vector.h" @@ -139,8 +139,8 @@ class RepackDesignConstraints { /* Nets to constraint */ vtr::vector repack_design_constraint_nets_; - - std::map> ignore_net_pin_map_; // std::set + + std::map> ignore_net_pin_map_; }; #endif From 539d41f3dfd9c196582a4d77431c4fc207b55939 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Wed, 29 Nov 2023 17:42:13 -0800 Subject: [PATCH 09/26] reformat the code --- libs/libpcf/src/base/repack_design_constraints.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 0dc058628..1f6a33e9b 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -140,7 +140,7 @@ class RepackDesignConstraints { vtr::vector repack_design_constraint_nets_; - std::map> ignore_net_pin_map_; + std::map> ignore_net_pin_map_; }; #endif From a50b007d72105c14e51d07ffff8d6480026d89ee Mon Sep 17 00:00:00 2001 From: ubuntu Date: Fri, 1 Dec 2023 03:02:52 -0800 Subject: [PATCH 10/26] add vtr assert --- libs/libpcf/src/base/repack_design_constraints.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index 8a3fa7f76..d1ea1f004 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -162,6 +162,7 @@ void RepackDesignConstraints::set_ignore_net_pin_map_( std::string("Invalid content '") + pin_ctx + std::string("' to skip, expect .\n"); VTR_LOG_ERROR(err_msg.c_str()); + VTR_ASSERT(pin_info.size() == 2); return; } std::string pb_type_name = pin_info[0]; @@ -172,6 +173,7 @@ void RepackDesignConstraints::set_ignore_net_pin_map_( std::string("Invalid pin definition '") + pin_ctx + std::string("', expect .[int:int]\n"); VTR_LOG_ERROR(err_msg.c_str()); + VTR_ASSERT(curr_port.is_valid()); return; } ignore_net_pin_map_[net_name].insert(pin_ctx); From 6055a42196039ef28772555c81eacb8dc3248285 Mon Sep 17 00:00:00 2001 From: ubuntu Date: Fri, 1 Dec 2023 03:04:32 -0800 Subject: [PATCH 11/26] add test case --- .../config/pin_constraints.xml | 5 ++ .../config/repack_design_constraints.xml | 7 +++ .../config/rst_on_lut_pc.xml | 5 ++ .../config/rst_on_lut_repack_dc.xml | 8 +++ .../repack_ignore_nets/config/task.conf | 50 +++++++++++++++++++ 5 files changed, 75 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml new file mode 100644 index 000000000..e297abb77 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/pin_constraints.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml new file mode 100644 index 000000000..d3fc31c4c --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml new file mode 100644 index 000000000..00b4b2bd6 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_pc.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml new file mode 100644 index 000000000..73436da74 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf new file mode 100644 index 000000000..63ffd257c --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf @@ -0,0 +1,50 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml +openfpga_vpr_device_layout=2x2 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localRstGen_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = two_dff_inv_rst +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints.xml +bench0_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml + +bench1_top = rst_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml +bench1_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 7475a002b613c3a47ace2ce7f3cd7384a6a5f016 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Mon, 4 Dec 2023 13:33:55 -0800 Subject: [PATCH 12/26] Update repack_design_constraints.xml by changing the separater between pb type and pin name To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error. --- .../repack_ignore_nets/config/repack_design_constraints.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml index d3fc31c4c..7c329b3e6 100644 --- a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml @@ -1,7 +1,7 @@ - + From a1169beaf0ad92b4c39018db872389a75584e6e9 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Mon, 4 Dec 2023 13:34:49 -0800 Subject: [PATCH 13/26] Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error. --- .../repack_ignore_nets/config/rst_on_lut_repack_dc.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml index 73436da74..71153e425 100644 --- a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml +++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml @@ -1,7 +1,7 @@ - + From d0958fc017d41f8e45e6898149ecb508c1b75b7a Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:09:45 -0800 Subject: [PATCH 14/26] Update repack_design_constraints.h --- libs/libpcf/src/base/repack_design_constraints.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 1f6a33e9b..46a18071c 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -6,7 +6,6 @@ *******************************************************************/ #include #include -#include #include /* Headers from vtrutil library */ #include "vtr_geometry.h" @@ -36,7 +35,7 @@ constexpr const char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN"; *******************************************************************/ class RepackDesignConstraints { public: /* Type of design constraints */ - enum e_design_constraint_type { PIN_ASSIGNMENT, NUM_DESIGN_CONSTRAINT_TYPES }; + enum e_design_constraint_type { PIN_ASSIGNMENT, IGNORE_NET, NUM_DESIGN_CONSTRAINT_TYPES }; public: /* Types */ typedef vtr::vector Date: Tue, 5 Dec 2023 09:17:29 -0800 Subject: [PATCH 15/26] Update repack_design_constraints.cpp --- .../src/base/repack_design_constraints.cpp | 38 ------------------- 1 file changed, 38 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index d1ea1f004..089aa8fe0 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -56,17 +56,6 @@ std::string RepackDesignConstraints::net( return repack_design_constraint_nets_[repack_design_constraint_id]; } -std::set RepackDesignConstraints::ignore_net_on_pin( - const std::string& net_name) const { - std::map>::const_iterator it = - ignore_net_pin_map_.find(net_name); - if (it != ignore_net_pin_map_.end()) { - return it->second; - } else { - return std::set(); - } -} - std::string RepackDesignConstraints::find_constrained_pin_net( const std::string& pb_type, const openfpga::BasicPort& pin) const { std::string constrained_net_name; @@ -151,33 +140,6 @@ void RepackDesignConstraints::set_net( repack_design_constraint_nets_[repack_design_constraint_id] = net; } -void RepackDesignConstraints::set_ignore_net_pin_map_( - const std::string& net_name, const std::string pin_ctx) { - /* Extract the pb_type name and port name */ - openfpga::StringToken pin_tokenizer(pin_ctx); - std::vector pin_info = pin_tokenizer.split('.'); - /* Expect two contents, otherwise error out */ - if (pin_info.size() != 2) { - std::string err_msg = - std::string("Invalid content '") + pin_ctx + - std::string("' to skip, expect .\n"); - VTR_LOG_ERROR(err_msg.c_str()); - VTR_ASSERT(pin_info.size() == 2); - return; - } - std::string pb_type_name = pin_info[0]; - openfpga::PortParser port_parser(pin_info[1]); - openfpga::BasicPort curr_port = port_parser.port(); - if (!curr_port.is_valid()) { - std::string err_msg = - std::string("Invalid pin definition '") + pin_ctx + - std::string("', expect .[int:int]\n"); - VTR_LOG_ERROR(err_msg.c_str()); - VTR_ASSERT(curr_port.is_valid()); - return; - } - ignore_net_pin_map_[net_name].insert(pin_ctx); -} /************************************************************************ * Internal invalidators/validators ***********************************************************************/ From 7aa882f82cd662ec5783809e491e143ec0f4b207 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:26:05 -0800 Subject: [PATCH 16/26] Update read_xml_repack_design_constraints.cpp --- .../io/read_xml_repack_design_constraints.cpp | 55 +++++++++++++++++-- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp b/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp index f3975d8cd..6e675d08d 100644 --- a/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp +++ b/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp @@ -11,6 +11,7 @@ /* Headers from vtr util library */ #include "vtr_assert.h" +#include "vtr_log.h" #include "vtr_time.h" /* Headers from libopenfpga util library */ @@ -52,6 +53,49 @@ static void read_xml_pin_constraint( get_attribute(xml_pin_constraint, "net", loc_data).as_string()); } +static void read_xml_ignore_net_constraint( + pugi::xml_node& xml_pin_constraint, const pugiutil::loc_data& loc_data, + RepackDesignConstraints& repack_design_constraints) { + /* Create a new design constraint in the storage */ + RepackDesignConstraintId design_constraint_id = + repack_design_constraints.create_design_constraint( + RepackDesignConstraints::IGNORE_NET); + + if (false == repack_design_constraints.valid_design_constraint_id( + design_constraint_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), + "Fail to create design constraint!\n"); + } + + std::string pin_ctx_to_parse = + get_attribute(xml_pin_constraint, "pin", loc_data).as_string(); + openfpga::StringToken pin_tokenizer(pin_ctx_to_parse); + std::vector pin_info = pin_tokenizer.split('.'); + /* Expect two contents, otherwise error out */ + if (pin_info.size() != 2) { + std::string err_msg = + std::string("Invalid content '") + pin_ctx_to_parse + + std::string("' to skip, expect .\n"); + VTR_LOG_ERROR(err_msg.c_str()); + VTR_ASSERT(pin_info.size() == 2); + } + std::string pb_type_name = pin_info[0]; + openfpga::PortParser port_parser(pin_info[1]); + openfpga::BasicPort curr_port = port_parser.port(); + if (!curr_port.is_valid()) { + std::string err_msg = + std::string("Invalid pin definition '") + pin_ctx_to_parse + + std::string("', expect .[int:int]\n"); + VTR_LOG_ERROR(err_msg.c_str()); + VTR_ASSERT(curr_port.is_valid()); + } + repack_design_constraints.set_pb_type(design_constraint_id, pb_type_name); + repack_design_constraints.set_pin(design_constraint_id, curr_port); + repack_design_constraints.set_net( + design_constraint_id, + get_attribute(xml_pin_constraint, "name", loc_data).as_string()); +} + /******************************************************************** * Parse XML codes about to an object of *RepackDesignConstraints @@ -83,13 +127,12 @@ RepackDesignConstraints read_xml_repack_design_constraints( if (xml_design_constraint.name() == std::string("pin_constraint")) { read_xml_pin_constraint(xml_design_constraint, loc_data, repack_design_constraints); - } else if (xml_design_constraint.name() == std::string("ignore_net")) { - repack_design_constraints.set_ignore_net_pin_map_( - get_attribute(xml_design_constraint, "name", loc_data).as_string(), - get_attribute(xml_design_constraint, "pin", loc_data).as_string()); + } else if (xml_design_constraint.name() == + std::string("ignore_net")) { + read_xml_ignore_net_constraint(xml_design_constraint, loc_data, + repack_design_constraints); } else { - bad_tag(xml_design_constraint, loc_data, xml_root, - {"pin_constraint", "ignore_net"}); + bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint", "ignore_net"}); } } } catch (pugiutil::XmlError& e) { From 83fdaea13da44dbafc8eb090feecca24e4c128f2 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:28:27 -0800 Subject: [PATCH 17/26] Update repack.cpp --- openfpga/src/repack/repack.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 35f45d7a1..6a6bbae2f 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -578,8 +578,7 @@ static void add_lb_router_nets( if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id) && clustering_ctx.clb_nlist.net_is_global(cluster_net_id) && options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), - curr_pin)) || - (options.net_is_specified_to_be_ignored( + curr_pin)) || (options.net_is_specified_to_be_ignored( atom_ctx.nlist.net_name(pb_pin_mapped_nets[source_pb_pin]), std::string(lb_type->pb_type->name), curr_pin))) { /* Find the net mapped to this pin in clustering results*/ From 231cb0f89b4310023b1efca0e873ea4ab3b14447 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:30:32 -0800 Subject: [PATCH 18/26] Update repack_option.cpp --- openfpga/src/repack/repack_option.cpp | 53 ++++++--------------------- 1 file changed, 11 insertions(+), 42 deletions(-) diff --git a/openfpga/src/repack/repack_option.cpp b/openfpga/src/repack/repack_option.cpp index 51581f072..af48ae2df 100644 --- a/openfpga/src/repack/repack_option.cpp +++ b/openfpga/src/repack/repack_option.cpp @@ -48,48 +48,17 @@ bool RepackOption::is_pin_ignore_global_nets(const std::string& pb_type_name, bool RepackOption::net_is_specified_to_be_ignored(std::string cluster_net_name, std::string pb_type_name, - const BasicPort& port) const { - auto pin_ctx_to_parse = - design_constraints_.ignore_net_on_pin(cluster_net_name); - if (pin_ctx_to_parse.empty()) { - /* Not found, return false */ - return false; - } else { - /* Split the content using a tokenizer */ - for (auto pin_ctx_to_parse_iter : pin_ctx_to_parse) { - int num_parse_errors_temp = 0; - StringToken tokenizer(pin_ctx_to_parse_iter); - std::vector tokens = tokenizer.split(','); - /* Parse each token */ - for (std::string token : tokens) { - /* Extract the pb_type name and port name */ - StringToken pin_tokenizer(token); - std::vector pin_info = pin_tokenizer.split('.'); - /* Expect two contents, otherwise error out */ - if (pin_info.size() != 2) { - std::string err_msg = - std::string("Invalid content '") + token + - std::string("' to skip, expect .\n"); - VTR_LOG_ERROR(err_msg.c_str()); - num_parse_errors_temp++; - continue; - } - std::string curr_pb_type_name = pin_info[0]; - PortParser port_parser(pin_info[1]); - BasicPort curr_port = port_parser.port(); - if (!curr_port.is_valid()) { - std::string err_msg = - std::string("Invalid pin definition '") + token + - std::string("', expect .[int:int]\n"); - VTR_LOG_ERROR(err_msg.c_str()); - num_parse_errors_temp++; - continue; - } - if (curr_port.mergeable(port) && curr_port.contained(port) && - curr_pb_type_name == pb_type_name) { - return true; - } - } + const BasicPort& pin) const { + const RepackDesignConstraints& design_constraint = design_constraints(); + /* If found a constraint, record the net name */ + for (const RepackDesignConstraintId id_ : + design_constraint.design_constraints()) { + if (design_constraint.type(id_) == RepackDesignConstraints::IGNORE_NET && + design_constraint.pb_type(id_) == pb_type_name && + design_constraint.net(id_) == cluster_net_name) { + if (design_constraint.pin(id_).mergeable(pin) && + design_constraint.pin(id_).contained(pin)) + return true; } } return false; From d2379cfff6195a4986016b00f0282cf193bd43a4 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:34:34 -0800 Subject: [PATCH 19/26] Update repack_option.h --- openfpga/src/repack/repack_option.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga/src/repack/repack_option.h b/openfpga/src/repack/repack_option.h index 76868a83e..d3f02ede8 100644 --- a/openfpga/src/repack/repack_option.h +++ b/openfpga/src/repack/repack_option.h @@ -25,9 +25,9 @@ class RepackOption { /* Identify if a pin should ignore all the global nets */ bool is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const; - bool net_is_specified_to_be_ignored(std::string cluster_net_name, - std::string pb_type_name, - const BasicPort& port) const; + bool net_is_specified_to_be_ignored( + std::string cluster_net_name, std::string pb_type_name, + const BasicPort& pin) const; bool verbose_output() const; public: /* Public mutators */ From b76541030058be754b2702fd1083a0bcbf31b0dd Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:37:56 -0800 Subject: [PATCH 20/26] Update repack_design_constraints.cpp --- libs/libpcf/src/base/repack_design_constraints.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.cpp b/libs/libpcf/src/base/repack_design_constraints.cpp index 089aa8fe0..220a2d41c 100644 --- a/libs/libpcf/src/base/repack_design_constraints.cpp +++ b/libs/libpcf/src/base/repack_design_constraints.cpp @@ -2,8 +2,6 @@ #include -#include "openfpga_port_parser.h" -#include "openfpga_tokenizer.h" #include "vtr_assert.h" #include "vtr_log.h" From 57f3b7af0fe669c639c7432013a558628dc21b24 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:38:27 -0800 Subject: [PATCH 21/26] Update repack_design_constraints.h --- libs/libpcf/src/base/repack_design_constraints.h | 1 + 1 file changed, 1 insertion(+) diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 46a18071c..996503ec2 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -7,6 +7,7 @@ #include #include #include + /* Headers from vtrutil library */ #include "vtr_geometry.h" #include "vtr_vector.h" From aa51b6d3881ca286351c6bb1cc23911ebba183b9 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 09:40:25 -0800 Subject: [PATCH 22/26] Update repack_design_constraints.h --- libs/libpcf/src/base/repack_design_constraints.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 996503ec2..564d5fb9d 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -69,7 +69,6 @@ class RepackDesignConstraints { std::string net( const RepackDesignConstraintId& repack_design_constraint_id) const; - std::set ignore_net_on_pin(const std::string& net_name) const; /* Find a constrained net */ std::string find_constrained_pin_net(const std::string& pb_type, const openfpga::BasicPort& pin) const; @@ -99,9 +98,6 @@ class RepackDesignConstraints { void set_net(const RepackDesignConstraintId& repack_design_constraint_id, const std::string& net); - void set_ignore_net_pin_map_(const std::string& net_name, - const std::string pin_ctx); - public: /* Public invalidators/validators */ bool valid_design_constraint_id( const RepackDesignConstraintId& repack_design_constraint_id) const; @@ -139,8 +135,6 @@ class RepackDesignConstraints { /* Nets to constraint */ vtr::vector repack_design_constraint_nets_; - - std::map> ignore_net_pin_map_; }; #endif From e6c9d22ce9208ea1ce47cde113ed7639d28dd6c7 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 10:10:19 -0800 Subject: [PATCH 23/26] Update repack_design_constraints.h code clean up --- libs/libpcf/src/base/repack_design_constraints.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/libs/libpcf/src/base/repack_design_constraints.h b/libs/libpcf/src/base/repack_design_constraints.h index 564d5fb9d..55ddbca7f 100644 --- a/libs/libpcf/src/base/repack_design_constraints.h +++ b/libs/libpcf/src/base/repack_design_constraints.h @@ -36,7 +36,11 @@ constexpr const char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN"; *******************************************************************/ class RepackDesignConstraints { public: /* Type of design constraints */ - enum e_design_constraint_type { PIN_ASSIGNMENT, IGNORE_NET, NUM_DESIGN_CONSTRAINT_TYPES }; + enum e_design_constraint_type { + PIN_ASSIGNMENT, + IGNORE_NET, + NUM_DESIGN_CONSTRAINT_TYPES + }; public: /* Types */ typedef vtr::vector Date: Tue, 5 Dec 2023 10:13:53 -0800 Subject: [PATCH 24/26] Update read_xml_repack_design_constraints.cpp code clean up --- libs/libpcf/src/io/read_xml_repack_design_constraints.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp b/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp index 6e675d08d..67b9435a7 100644 --- a/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp +++ b/libs/libpcf/src/io/read_xml_repack_design_constraints.cpp @@ -127,12 +127,12 @@ RepackDesignConstraints read_xml_repack_design_constraints( if (xml_design_constraint.name() == std::string("pin_constraint")) { read_xml_pin_constraint(xml_design_constraint, loc_data, repack_design_constraints); - } else if (xml_design_constraint.name() == - std::string("ignore_net")) { + } else if (xml_design_constraint.name() == std::string("ignore_net")) { read_xml_ignore_net_constraint(xml_design_constraint, loc_data, repack_design_constraints); } else { - bad_tag(xml_design_constraint, loc_data, xml_root, {"pin_constraint", "ignore_net"}); + bad_tag(xml_design_constraint, loc_data, xml_root, + {"pin_constraint", "ignore_net"}); } } } catch (pugiutil::XmlError& e) { From 94f7b2f4e2f4b09b7262762b83c688d4ffdf3dcf Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 10:16:10 -0800 Subject: [PATCH 25/26] Update repack.cpp code clean up --- openfpga/src/repack/repack.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 6a6bbae2f..35f45d7a1 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -578,7 +578,8 @@ static void add_lb_router_nets( if ((clustering_ctx.clb_nlist.net_is_ignored(cluster_net_id) && clustering_ctx.clb_nlist.net_is_global(cluster_net_id) && options.is_pin_ignore_global_nets(std::string(lb_type->pb_type->name), - curr_pin)) || (options.net_is_specified_to_be_ignored( + curr_pin)) || + (options.net_is_specified_to_be_ignored( atom_ctx.nlist.net_name(pb_pin_mapped_nets[source_pb_pin]), std::string(lb_type->pb_type->name), curr_pin))) { /* Find the net mapped to this pin in clustering results*/ From 8a24b1ba8ce8030e64f09932ba8b550c59b008a6 Mon Sep 17 00:00:00 2001 From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com> Date: Tue, 5 Dec 2023 10:17:52 -0800 Subject: [PATCH 26/26] Update repack_option.h code clean up --- openfpga/src/repack/repack_option.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga/src/repack/repack_option.h b/openfpga/src/repack/repack_option.h index d3f02ede8..9fdb3392f 100644 --- a/openfpga/src/repack/repack_option.h +++ b/openfpga/src/repack/repack_option.h @@ -25,9 +25,9 @@ class RepackOption { /* Identify if a pin should ignore all the global nets */ bool is_pin_ignore_global_nets(const std::string& pb_type_name, const BasicPort& pin) const; - bool net_is_specified_to_be_ignored( - std::string cluster_net_name, std::string pb_type_name, - const BasicPort& pin) const; + bool net_is_specified_to_be_ignored(std::string cluster_net_name, + std::string pb_type_name, + const BasicPort& pin) const; bool verbose_output() const; public: /* Public mutators */