Merge branch 'master' into preloading_clean

VERSION.md

@@ -1 +1 @@
-1.2.2710
+1.2.2739

docs/source/manual/file_formats/index.rst

@@ -45,3 +45,5 @@ OpenFPGA widely uses XML format for interchangeable files
    fabric_pin_physical_location_file
 
    fabric_hierarchy_file
+
+   reference_file

docs/source/manual/file_formats/reference_file.rst

@@ -0,0 +1,80 @@
+.. _file_format_reference_file:
+
+Reference File (.yaml)
+----------------------------------------
+
+This file is generated by command :ref:`openfpga_setup_commands_report_reference`
+
+
+The reference file aims to the show reference number of each child module of given parent module
+
+By using the options of the command :ref:`openfpga_setup_commands_report_reference`, user can selectively output the reference info under the given parent module on their needs.
+
+An example of the file is shown as follows.
+
+.. code-block:: yaml
+
+Date: Mon Sep  9 16:41:53 2024
+
+#the instance names are given during netlist generation
+references:
+- module: grid_io_top
+  count: 1
+  instances:
+    - grid_io_top_1__2_
+- module: grid_io_right
+  count: 1
+  instances:
+    - grid_io_right_2__1_
+- module: grid_io_bottom
+  count: 1
+  instances:
+    - grid_io_bottom_1__0_
+- module: grid_io_left
+  count: 1
+  instances:
+    - grid_io_left_0__1_
+- module: grid_clb
+  count: 1
+  instances:
+    - grid_clb_1__1_
+- module: sb_0__0_
+  count: 1
+  instances:
+    - sb_0__0_
+- module: sb_0__1_
+  count: 1
+  instances:
+    - sb_0__1_
+- module: sb_1__0_
+  count: 1
+  instances:
+    - sb_1__0_
+- module: sb_1__1_
+  count: 1
+  instances:
+    - sb_1__1_
+- module: cbx_1__0_
+  count: 1
+  instances:
+    - cbx_1__0_
+- module: cbx_1__1_
+  count: 1
+  instances:
+    - cbx_1__1_
+- module: cby_0__1_
+  count: 1
+  instances:
+    - cby_0__1_
+- module: cby_1__1_
+  count: 1
+  instances:
+    - cby_1__1_
+          direct_interc
+
+In this example, the parent module is ``fpga_top``.
+The child modules under ``fpga_top`` are ``grid_io_top``, ``grid_io_right``, and etc.
+
+The instance of the child module ``grid_io_top`` is shown as a list as below:
+    - grid_io_top_1__2_
+

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -235,6 +235,10 @@ pb_pin_fixup
   .. warning:: This feature has been integrated into VPR to provide accurate timing analysis results at post-routing stage. However, this command provides a light fix-up (not as thorough as the one in VPR) but bring more flexibility in support some architecture without local routing. Suggest to enable it when your architecture does not have local routing for *Look-Up Tables* (LUTs) but you want to enable logic equivalent for input pins of LUTs
 
   .. warning:: This command may be deprecated in future
+
+  .. option:: --map_global_net_to_msb
+
+    If specified, any global net including clock, reset etc, will be mapped to a best-fit Most Significant Bit (MSB) of input ports of programmable blocks. If not specified, a best-fit Least Significant Bit (LSB) will be the default choice. For example, when ``--clock_modeling ideal`` is selected when running VPR, global nets will not be routed and their pin mapping on programmable blocks may be revoked by other nets due to optimization. Therefore, this command will restore the pin mapping for the global nets and pick a spare pin on programmable blocks. This option is to set a preference when mapping the global nets to spare pins.
   
   .. option:: --verbose
 
@@ -521,3 +525,26 @@ write_fabric_pin_physical_location
   .. option:: --verbose
 
     Show verbose log
+
+.. _openfpga_setup_commands_report_reference:
+
+report_reference
+~~~~~~~~~~~~~~~~~~~~
+
+  Write reference information of each child module under a given parent module to a YAML file
+
+  .. option:: --file <string> or -f <string>
+
+    Specify the file name to write the reference information
+
+  .. option:: --module <string>
+
+    Specify the parent module name, under which the references of each child module will be reported.
+
+  .. option:: --no_time_stamp
+
+    Do not print time stamp in output files
+
+  .. option:: --verbose
+
+    Show verbose info

openfpga/src/base/openfpga_build_fabric_template.h

@@ -22,6 +22,7 @@
 #include "read_xml_tile_config.h"
 #include "read_xml_unique_blocks.h"
 #include "rename_modules.h"
+#include "report_reference.h"
 #include "vtr_log.h"
 #include "vtr_time.h"
 #include "write_xml_fabric_pin_physical_location.h"
@@ -478,14 +479,15 @@ int write_fabric_pin_physical_location_template(
     cmd_context.option_enable(cmd, opt_verbose));
 }
 
+
 template <class T>
 int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd,
                                 const CommandContext& cmd_context) {
   CommandOptionId opt_verbose = cmd.option("verbose");
   CommandOptionId opt_file = cmd.option("file");
   CommandOptionId opt_type = cmd.option("type");
-
+  
-  /* Check the option '--file' is enabled or not
+    /* Check the option '--file' is enabled or not
    * Actually, it must be enabled as the shell interface will check
    * before reaching this fuction
    */
@@ -518,10 +520,9 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd,
    */
   VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
   VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
-
+  
   std::string file_name = cmd_context.option_value(cmd, opt_file);
   std::string file_type = cmd_context.option_value(cmd, opt_type);
-
   /* Write unique blocks to a file */
   /* add check flag */
   if (file_type == "xml") {
@@ -533,6 +534,35 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd,
     return CMD_EXEC_FATAL_ERROR;
   }
 }
+  
+
+/********************************************************************
+ *  Report reference to a file
+ *******************************************************************/
+template <class T>
+int report_reference_template(const T& openfpga_ctx, const Command& cmd,
+                              const CommandContext& cmd_context) {
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
+
+  CommandOptionId opt_file = cmd.option("file");
+
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+  std::string file_name = cmd_context.option_value(cmd, opt_file);
+
+  std::string module_name("*"); /* Use a wildcard for everything */
+  CommandOptionId opt_module = cmd.option("module");
+  if (true == cmd_context.option_enable(cmd, opt_module)) {
+    module_name = cmd_context.option_value(cmd, opt_module);
+  }
+  /* Write hierarchy to a file */
+  return report_reference(file_name.c_str(), module_name,
+                          openfpga_ctx.module_graph(),
+                          !cmd_context.option_enable(cmd, opt_no_time_stamp),
+                          cmd_context.option_enable(cmd, opt_verbose));
+}
+
 } /* end namespace openfpga */
 
 #endif

openfpga/src/base/openfpga_pb_pin_fixup.cpp

@@ -32,8 +32,8 @@ namespace openfpga {
 static int update_cluster_pin_global_net_with_post_routing_results(
   const ClusteringContext& clustering_ctx,
   VprClusteringAnnotation& clustering_annotation, const ClusterBlockId& blk_id,
-  t_logical_block_type_ptr logical_block, size_t& num_fixup,
+  t_logical_block_type_ptr logical_block, const bool& map_gnet2msb,
-  const bool& verbose) {
+  size_t& num_fixup, const bool& verbose) {
   /* Reassign global nets to unused pins in the same port where they were mapped
    * NO optimization is done here!!! First find first fit
    */
@@ -77,10 +77,13 @@ static int update_cluster_pin_global_net_with_post_routing_results(
       "during routing optimization\n",
       clustering_ctx.clb_nlist.net_name(global_net_id).c_str());
     size_t cand_pin_start = pb_type_pin - pb_graph_pin->pin_number;
-    size_t cand_pin_end = cand_pin_start + pb_graph_pin->port->num_pins;
+    std::vector<size_t> cand_pins(pb_graph_pin->port->num_pins);
+    std::iota(cand_pins.begin(), cand_pins.end(), cand_pin_start);
+    if (map_gnet2msb) {
+      std::reverse(cand_pins.begin(), cand_pins.end());
+    }
     bool found_cand = false;
-    for (size_t cand_pin = cand_pin_start; cand_pin < cand_pin_end;
+    for (size_t cand_pin : cand_pins) {
-         ++cand_pin) {
       ClusterNetId cand_pin_net_id =
         clustering_ctx.clb_nlist.block_net(blk_id, cand_pin);
       const t_pb_graph_pin* cand_pb_graph_pin =
@@ -139,7 +142,7 @@ static int update_cluster_pin_with_post_routing_results(
   VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer,
   const vtr::Point<size_t>& grid_coord, const ClusterBlockId& blk_id,
   const e_side& border_side, const size_t& z, const bool& perimeter_cb,
-  size_t& num_fixup, const bool& verbose) {
+  const bool& map_gnet2msb, size_t& num_fixup, const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
   /* Handle each pin */
   auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
@@ -337,8 +340,8 @@ static int update_cluster_pin_with_post_routing_results(
   }
   /* 2nd round of fixup: focus on global nets */
   status = update_cluster_pin_global_net_with_post_routing_results(
-    clustering_ctx, vpr_clustering_annotation, blk_id, logical_block, num_fixup,
+    clustering_ctx, vpr_clustering_annotation, blk_id, logical_block,
-    verbose);
+    map_gnet2msb, num_fixup, verbose);
   return status;
 }
 
@@ -351,9 +354,12 @@ int update_pb_pin_with_post_routing_results(
   const PlacementContext& placement_ctx,
   const VprRoutingAnnotation& vpr_routing_annotation,
   VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
-  const bool& verbose) {
+  const bool& map_gnet2msb, const bool& verbose) {
   int status = CMD_EXEC_SUCCESS;
   size_t num_fixup = 0;
+  /* Confirm options */
+  VTR_LOGV(verbose && map_gnet2msb,
+           "User choose to map global net to the best fit MSB of input port\n");
   /* Ensure a clean start: remove all the remapping results from VTR's
    * post-routing clustering result sync-up */
   vpr_clustering_annotation.clear_net_remapping();
@@ -384,7 +390,7 @@ int update_pb_pin_with_post_routing_results(
           device_ctx, clustering_ctx, vpr_routing_annotation,
           vpr_clustering_annotation, layer, grid_coord, cluster_blk_id,
           NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile,
-          perimeter_cb, num_fixup, verbose);
+          perimeter_cb, map_gnet2msb, num_fixup, verbose);
         if (status != CMD_EXEC_SUCCESS) {
           return CMD_EXEC_FATAL_ERROR;
         }
@@ -419,7 +425,7 @@ int update_pb_pin_with_post_routing_results(
           device_ctx, clustering_ctx, vpr_routing_annotation,
           vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side,
           placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, perimeter_cb,
-          num_fixup, verbose);
+          map_gnet2msb, num_fixup, verbose);
         if (status != CMD_EXEC_SUCCESS) {
           return CMD_EXEC_FATAL_ERROR;
         }

openfpga/src/base/openfpga_pb_pin_fixup.h

@@ -19,7 +19,7 @@ int update_pb_pin_with_post_routing_results(
   const PlacementContext& placement_ctx,
   const VprRoutingAnnotation& vpr_routing_annotation,
   VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
-  const bool& verbose);
+  const bool& map_gnet2msb, const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/base/openfpga_pb_pin_fixup_template.h

@@ -35,6 +35,7 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd,
   vtr::ScopedStartFinishTimer timer(
     "Fix up pb pin mapping results after routing optimization");
 
+  CommandOptionId opt_map_gnet2msb = cmd.option("map_global_net_to_msb");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* Apply fix-up to each grid */
@@ -43,6 +44,7 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd,
     openfpga_context.vpr_routing_annotation(),
     openfpga_context.mutable_vpr_clustering_annotation(),
     g_vpr_ctx.device().arch->perimeter_cb,
+    cmd_context.option_enable(cmd, opt_map_gnet2msb),
     cmd_context.option_enable(cmd, opt_verbose));
 }
 

openfpga/src/base/openfpga_setup_command_template.h

@@ -324,6 +324,13 @@ ShellCommandId add_pb_pin_fixup_command_template(
   const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
   Command shell_cmd("pb_pin_fixup");
 
+  /* Add an option '--map_global_net_to_msb' */
+  shell_cmd.add_option(
+    "map_global_net_to_msb", false,
+    "If specified, any global net including clock, reset etc, will be mapped "
+    "to a best-fit Most Significant Bit (MSB) of input ports of programmable "
+    "blocks. If not specified, a best-fit Least Significant Bit (LSB) will be "
+    "the default choice");
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Show verbose outputs");
 
@@ -932,7 +939,7 @@ ShellCommandId add_write_fabric_pin_physical_location_command_template(
 
 /********************************************************************
  * - Add a command to Shell environment: read_unique_blocks
- * - Add associated options
+  * - Add associated options
  * - Add command dependency
  *******************************************************************/
 template <class T>
@@ -1002,7 +1009,51 @@ ShellCommandId add_write_unique_blocks_command_template(
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_execute_function(shell_cmd_id,
                                      write_unique_blocks_template<T>);
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
+  return shell_cmd_id;
+}
+
+ 
+ *******************************************************************/
+ * - Add a command to Shell environment: report_reference
+ * - Add associated options
+ * - Add command dependency
+ *******************************************************************/
+template <class T>
+ShellCommandId add_report_reference_command_template(
+  openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
+  const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
+  Command shell_cmd("report_reference");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId opt_file =
+    shell_cmd.add_option("file", true, "specify the file to output results");
+  shell_cmd.set_option_short_name(opt_file, "f");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--module'*/
+  CommandOptionId opt_module =
+    shell_cmd.add_option("module", false,
+                         "specify the module under which the references of "
+                         "child modules will be reported");
+  shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING);
+
+  /* Add an option '--no_time_stamp' */
+  shell_cmd.add_option("no_time_stamp", false,
+                       "do not print time stamp in output files");
+
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command to the Shell */
+  ShellCommandId shell_cmd_id =
+    shell.add_command(shell_cmd,
+                      "report all instances of each unique module, "
+                      "under a given module",
+                      hidden);
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_const_execute_function(shell_cmd_id,
+                                           report_reference_template<T>);
   /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
@@ -1261,6 +1312,16 @@ void add_setup_command_templates(openfpga::Shell<T>& shell,
     shell, openfpga_setup_cmd_class,
     cmd_dependency_write_fabric_pin_physical_location, hidden);
 
+  /********************************
+   * Command 'report_reference'
+   */
+  /* The command should NOT be executed before 'build_fabric' */
+  std::vector<ShellCommandId> cmd_dependency_report_reference;
+  cmd_dependency_report_reference.push_back(build_fabric_cmd_id);
+  add_report_reference_command_template<T>(
+    shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden);
+}
+
   /********************************
    * Command 'read_unique_blocks'
    */

openfpga/src/utils/report_reference.cpp

@@ -0,0 +1,123 @@
+/***************************************************************************************
+ * Output internal structure of module graph to XML format
+ ***************************************************************************************/
+/* Headers from system goes first */
+#include <algorithm>
+#include <chrono>
+#include <ctime>
+#include <iomanip>
+#include <string>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from openfpgautil library */
+#include "command_exit_codes.h"
+#include "openfpga_digest.h"
+#include "openfpga_naming.h"
+#include "report_reference.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Top-level function
+ *******************************************************************/
+int report_reference(const char* fname, const std::string& module_name,
+                     const ModuleManager& module_manager,
+                     const bool& include_time_stamp, const bool& verbose) {
+  vtr::ScopedStartFinishTimer timer("Report reference");
+
+  ModuleId parent_module = module_manager.find_module(module_name);
+  if (false == module_manager.valid_module_id(parent_module)) {
+    VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str());
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  show_reference_count(parent_module, module_manager);
+
+  return write_reference_to_file(fname, parent_module, module_manager,
+                                 include_time_stamp, verbose);
+}
+
+/********************************************************************
+ * show reference count of each child module under given parent module
+ *******************************************************************/
+void show_reference_count(const ModuleId& parent_module,
+                          const ModuleManager& module_manager) {
+  VTR_LOG(
+    "----------------------------------------------------------------------\n");
+  VTR_LOG(
+    "Module                                  Count                         \n");
+  VTR_LOG(
+    "--------------------------------------------------------------------- \n");
+  size_t ref_cnt = 0;
+  for (ModuleId child_module : module_manager.child_modules(parent_module)) {
+    std::string child_module_name = module_manager.module_name(child_module);
+    std::vector<size_t> child_inst_vec =
+      module_manager.child_module_instances(parent_module, child_module);
+    VTR_LOG("%-s   %d\n", child_module_name.c_str(), child_inst_vec.size());
+    ref_cnt += child_inst_vec.size();
+  }
+  VTR_LOG(
+    "----------------------------------------------------------------------\n");
+  VTR_LOG("Total: %zu modules %zu references\n",
+          module_manager.child_modules(parent_module).size(), ref_cnt);
+  VTR_LOG(
+    "----------------------------------------------------------------------\n");
+}
+
+/********************************************************************
+ * write reference info to a given file in YAML format
+ *******************************************************************/
+int write_reference_to_file(const char* fname, const ModuleId& parent_module,
+                            const ModuleManager& module_manager,
+                            const bool& include_time_stamp,
+                            const bool& verbose) {
+  std::fstream fp;
+  fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
+  openfpga::check_file_stream(fname, fp);
+
+  if (include_time_stamp) {
+    auto end = std::chrono::system_clock::now();
+    std::time_t end_time = std::chrono::system_clock::to_time_t(end);
+    fp << "Date: " << std::ctime(&end_time) << std::endl;
+  }
+
+  fp << "#the instance names are given during netlist generation" << std::endl;
+
+  size_t ref_cnt = 0;
+  fp << "references:" << std::endl;
+  for (ModuleId child_module : module_manager.child_modules(parent_module)) {
+    std::string child_module_name = module_manager.module_name(child_module);
+    std::vector<size_t> child_inst_vec =
+      module_manager.child_module_instances(parent_module, child_module);
+    fp << "- module: " << child_module_name.c_str() << std::endl
+       << "  count: " << child_inst_vec.size() << std::endl
+       << "  instances:" << std::endl;
+    for (size_t inst_id : child_inst_vec) {
+      std::string inst_name =
+        module_manager.instance_name(parent_module, child_module, inst_id);
+      fp << "    - ";
+      if (true == inst_name.empty()) {
+        fp << generate_instance_name(child_module_name, inst_id) << std::endl;
+      } else {
+        fp << inst_name << std::endl;
+      }
+    }
+    ref_cnt += child_inst_vec.size();
+  }
+
+  if (verbose) {
+    fp << std::endl
+       << "Total: " << module_manager.child_modules(parent_module).size()
+       << " modules " << ref_cnt << " references" << std::endl;
+  }
+
+  fp.close();
+  return CMD_EXEC_SUCCESS;
+}
+
+} /* end namespace openfpga */

openfpga/src/utils/report_reference.h

@@ -0,0 +1,30 @@
+#ifndef REPORT_REFERENCE_H
+#define REPORT_REFERENCE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+int report_reference(const char* fname, const std::string& module_name,
+                     const ModuleManager& module_manager,
+                     const bool& include_time_stamp, const bool& verbose);
+
+void show_reference_count(const ModuleId& parent_module,
+                          const ModuleManager& module_manager);
+
+int write_reference_to_file(const char* fname, const ModuleId& parent_module,
+                            const ModuleManager& module_manager,
+                            const bool& include_time_stamp,
+                            const bool& verbose);
+} /* end namespace openfpga */
+
+#endif

openfpga/src/vpr_wrapper/vpr_main.cpp

@@ -68,7 +68,7 @@ static int vpr(int argc, char** argv) {
      */
     /* vpr_free_all(Arch, vpr_setup); */
 
-    VTR_LOG("VPR suceeded\n");
+    VTR_LOG("VPR succeeded\n");
 
   } catch (const tatum::Error& tatum_error) {
     VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str());

openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga

@@ -22,7 +22,7 @@ append_clock_rr_graph
 # to debug use --verbose options
 link_openfpga_arch --sort_gsb_chan_node_in_edges
 
-pb_pin_fixup --verbose
+pb_pin_fixup ${OPENFPGA_PB_PIN_FIXUP_OPTIONS}
 
 # Route clock based on clock network definition
 route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}

openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga

@@ -0,0 +1,37 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enabled frame view creation to save runtime and memory
+#    Note that this is turned on when bitstream generation 
+#    is the ONLY purpose of the flow!!!
+build_fabric --compress_routing --frame_view #--verbose
+
+# Report reference to a file
+report_reference ${OPENFPGA_REPORT_REFERENCE_MODULE_OPTIONS}
+report_reference ${OPENFPGA_REPORT_REFERENCE_VERBOSE_OPTIONS}
+report_reference ${OPENFPGA_REPORT_REFERENCE_NO_TIME_STAMP_OPTIONS}
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -258,6 +258,7 @@ run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unus
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@
+run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@
 run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@
@@ -322,6 +323,10 @@ run-task basic_tests/no_time_stamp/device_1x1 $@
 run-task basic_tests/no_time_stamp/device_4x4 $@
 run-task basic_tests/no_time_stamp/no_cout_in_gsb $@
 run-task basic_tests/no_time_stamp/dump_waveform $@
+
+echo -e "Testing report reference to file";
+run-task basic_tests/report_reference $@
+
 # Run git-diff to ensure no changes on the golden netlists
 # Switch to root path in case users are running the tests in another location
 cd ${OPENFPGA_PATH}

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf

@@ -25,6 +25,7 @@ openfpga_vpr_route_chan_width=32
 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
 openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
 openfpga_route_clock_options=
+openfpga_pb_pin_fixup_options=--verbose
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml

@@ -0,0 +1,34 @@
+<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0"> 
+  <clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]"> 
+    <spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
+      <switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/> 
+      <switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/> 
+      <switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/> 
+      <switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/> 
+    </spine>  
+    <spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <taps>
+      <all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
+      <all from_pin="op_clk[0:0]" to_pin="clb[0:0].I[0:11]"/>
+    </taps>
+  </clock_network>  
+  <clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]"> 
+    <spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1"> 
+      <switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/> 
+      <switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/> 
+    </spine>  
+    <spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
+    <spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
+    <taps>
+      <all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
+      <all from_pin="op_reset[0:0]" to_pin="clb[0:0].I[0:11]"/>
+    </taps>
+  </clock_network>  
+</clock_networks> 

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml

@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="OPEN"/>
+  <set_io pin="op_clk[0]" net="clk"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml

@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="rst"/>
+  <set_io pin="op_clk[0]" net="clk"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml

@@ -0,0 +1,8 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="rst"/>
+  <set_io pin="op_clk[0]" net="clk"/>
+</pin_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml

@@ -0,0 +1,4 @@
+<repack_design_constraints>
+  <!-- Intended to be dummy -->
+</repack_design_constraints>
+

openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf

@@ -0,0 +1,57 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
+openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=32
+openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
+openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
+openfpga_route_clock_options=
+openfpga_pb_pin_fixup_options=--map_global_net_to_msb --verbose
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
+bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
+
+bench0_top = rst_on_lut
+bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst.xml
+
+bench1_top = clk_on_lut
+bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml
+
+bench2_top = rst_and_clk_on_lut
+bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/report_reference/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_report_reference_module_options=--file reference_module.yaml --module fpga_top
+openfpga_report_reference_verbose_options=--file reference_verbose.yaml --module fpga_top --verbose
+openfpga_report_reference_no_time_stamp_options=--file reference_no_time_stamp.yaml --module grid_io_right --no_time_stamp
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

yosys

@@ -1 +1 @@
-Subproject commit 0fc5812dcd0c62830f4faa27c4b62c03f3fd91ad
+Subproject commit 693724101280384479e0a3d15647a58a5e445a50