From 0093d4b269ca368a6241393a12f6a8125e8de1c7 Mon Sep 17 00:00:00 2001 From: Victor Date: Mon, 2 Sep 2024 15:21:50 +0800 Subject: [PATCH 01/20] Add command report_reference --- .../src/base/openfpga_build_fabric_template.h | 34 +++++++ .../base/openfpga_setup_command_template.h | 61 ++++++++++-- openfpga/src/utils/report_reference.cpp | 92 +++++++++++++++++++ openfpga/src/utils/report_reference.h | 24 +++++ 4 files changed, 205 insertions(+), 6 deletions(-) create mode 100644 openfpga/src/utils/report_reference.cpp create mode 100644 openfpga/src/utils/report_reference.h diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index b36903a22..988ac3117 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -24,6 +24,7 @@ #include "vtr_log.h" #include "vtr_time.h" #include "write_xml_fabric_pin_physical_location.h" +#include "report_reference.h" #include "write_xml_module_name_map.h" /* begin namespace openfpga */ @@ -472,6 +473,39 @@ int write_fabric_pin_physical_location_template( cmd_context.option_enable(cmd, opt_verbose)); } +/******************************************************************** + * Report reference to a file + *******************************************************************/ +template +int report_reference_template( + const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); + + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + CommandOptionId opt_file = cmd.option("file"); + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string file_name = cmd_context.option_value(cmd, opt_file); + + std::string module_name("*"); /* Use a wildcard for everything */ + CommandOptionId opt_module = cmd.option("module"); + if (true == cmd_context.option_enable(cmd, opt_module)) { + module_name = cmd_context.option_value(cmd, opt_module); + } + + /* Write hierarchy to a file */ + return report_reference( + file_name.c_str(), module_name, openfpga_ctx.module_graph(), + !cmd_context.option_enable(cmd, opt_no_time_stamp), + cmd_context.option_enable(cmd, opt_verbose)); +} + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 53e43f00f..3f66c9ebe 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -710,12 +710,6 @@ ShellCommandId add_route_clock_rr_graph_command_template( shell_cmd.set_option_short_name(opt_file, "pcf"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); - shell_cmd.add_option("disable_unused_trees", false, - "Disable entire clock trees when they are not used by " - "any clock nets. Useful to reduce clock power"); - shell_cmd.add_option("disable_unused_spines", false, - "Disable part of the clock tree which are used by clock " - "nets. Useful to reduce clock power"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); @@ -930,6 +924,50 @@ ShellCommandId add_write_fabric_pin_physical_location_command_template( return shell_cmd_id; } +/******************************************************************** + * - Add a command to Shell environment: report_reference + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_report_reference_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("report_reference"); + /* Add an option '--file' in short '-f'*/ + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, + "specify the file to output results"); + shell_cmd.set_option_short_name(opt_file, "f"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + + /* Add an option '--module'*/ + CommandOptionId opt_module = shell_cmd.add_option( + "module", false, + "specify the module under which the references of child modules will be reported"); + shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING); + + /* Add an option '--no_time_stamp' */ + shell_cmd.add_option("no_time_stamp", false, + "Do not print time stamp in output files"); + + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, + "report the number of instances for each unique module, under a given module", + hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_const_execute_function( + shell_cmd_id, report_reference_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + template void add_setup_command_templates(openfpga::Shell& shell, const bool& hidden = false) { @@ -1181,6 +1219,17 @@ void add_setup_command_templates(openfpga::Shell& shell, add_write_fabric_pin_physical_location_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_write_fabric_pin_physical_location, hidden); + + /******************************** + * Command 'report_reference' + */ + /* The command should NOT be executed before 'build_fabric' */ + std::vector cmd_dependency_report_reference; + cmd_dependency_report_reference.push_back( + build_fabric_cmd_id); + add_report_reference_command_template( + shell, openfpga_setup_cmd_class, + cmd_dependency_report_reference, hidden); } } /* end namespace openfpga */ diff --git a/openfpga/src/utils/report_reference.cpp b/openfpga/src/utils/report_reference.cpp new file mode 100644 index 000000000..e7e0cf9b7 --- /dev/null +++ b/openfpga/src/utils/report_reference.cpp @@ -0,0 +1,92 @@ +/*************************************************************************************** + * Output internal structure of module graph to XML format + ***************************************************************************************/ +/* Headers from system goes first */ +#include +#include +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from openfpgautil library */ +#include "command_exit_codes.h" +#include "openfpga_digest.h" + +#include "report_reference.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/******************************************************************** + * Top-level function + *******************************************************************/ +int report_reference(const char* fname, + const std::string& module_name, + const ModuleManager& module_manager, + const bool& include_time_stamp, + const bool& verbose) { + vtr::ScopedStartFinishTimer timer("Report reference"); + + std::fstream fp; + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + openfpga::check_file_stream(fname, fp); + + if (include_time_stamp) { + auto end = std::chrono::system_clock::now(); + std::time_t end_time = std::chrono::system_clock::to_time_t(end); + fp << "Date: " << std::ctime(&end_time) << std::endl; + } + + ModuleId parent_module = module_manager.find_module(module_name); + if (ModuleId::INVALID() == parent_module){ + VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str()); + return CMD_EXEC_MINOR_ERROR; + } + + if (module_manager.child_modules(parent_module).size() < 1){ + VTR_LOG_ERROR("Module %s hasn't any child module\n", module_name.c_str()); + return CMD_EXEC_MINOR_ERROR; + } + + VTR_LOG("------------------------------------------------------------------------------\n"); + VTR_LOG("Module Reference count\n"); + VTR_LOG("------------------------------------------------------------------------------\n"); + size_t ref_cnt = 0; + for (ModuleId child_module : module_manager.child_modules(parent_module)){ + std::string child_module_name = module_manager.module_name(child_module); + std::vector child_inst_vec = module_manager.child_module_instances(parent_module, child_module); + for (size_t pos = 0; pos < child_module_name.length(); pos += 70){ + if (pos > 0) VTR_LOG("\n"); + VTR_LOG("%-70s", child_module_name.substr(pos).c_str()); + } + VTR_LOG(" %7d\n", child_inst_vec.size()); + ref_cnt += child_inst_vec.size(); + } + VTR_LOG("------------------------------------------------------------------------------\n"); + VTR_LOG("Total %zu modules %zu references\n", module_manager.child_modules(parent_module).size(), ref_cnt); + VTR_LOG("------------------------------------------------------------------------------\n"); + + fp << "references:" << std::endl; + for (ModuleId child_module : module_manager.child_modules(parent_module)){ + std::string child_module_name = module_manager.module_name(child_module); + std::vector child_inst_vec = module_manager.child_module_instances(parent_module, child_module); + fp << "- module: " << child_module_name.c_str() << "\n" + << " reference count: " << child_inst_vec.size() << "\n" + << " instances:" << "\n"; + for (size_t inst_id : child_inst_vec){ + std::string inst_name = module_manager.instance_name(parent_module, child_module, inst_id); + fp << " - " << inst_name.c_str() << "\n"; + } + } + + fp.close(); + + return CMD_EXEC_SUCCESS; +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/utils/report_reference.h b/openfpga/src/utils/report_reference.h new file mode 100644 index 000000000..6bed89b90 --- /dev/null +++ b/openfpga/src/utils/report_reference.h @@ -0,0 +1,24 @@ +#ifndef REPORT_REFERENCE_H +#define REPORT_REFERENCE_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "module_manager.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/* begin namespace openfpga */ +namespace openfpga { +int report_reference(const char* fname, + const std::string& module_name, + const ModuleManager& module_manager, + const bool& include_time_stamp, + const bool& verbose); +} /* end namespace openfpga */ + +#endif From ba5c8a3364452d547f7fea74fafbccb6f01e32ce Mon Sep 17 00:00:00 2001 From: Victor Date: Tue, 3 Sep 2024 11:20:51 +0800 Subject: [PATCH 02/20] update code format --- .../src/base/openfpga_build_fabric_template.h | 15 +++-- .../base/openfpga_setup_command_template.h | 31 +++++----- openfpga/src/utils/report_reference.cpp | 56 +++++++++++-------- openfpga/src/utils/report_reference.h | 6 +- 4 files changed, 58 insertions(+), 50 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 988ac3117..bf1a292fa 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -21,10 +21,10 @@ #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" #include "rename_modules.h" +#include "report_reference.h" #include "vtr_log.h" #include "vtr_time.h" #include "write_xml_fabric_pin_physical_location.h" -#include "report_reference.h" #include "write_xml_module_name_map.h" /* begin namespace openfpga */ @@ -477,9 +477,8 @@ int write_fabric_pin_physical_location_template( * Report reference to a file *******************************************************************/ template -int report_reference_template( - const T& openfpga_ctx, const Command& cmd, - const CommandContext& cmd_context) { +int report_reference_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp"); @@ -500,10 +499,10 @@ int report_reference_template( } /* Write hierarchy to a file */ - return report_reference( - file_name.c_str(), module_name, openfpga_ctx.module_graph(), - !cmd_context.option_enable(cmd, opt_no_time_stamp), - cmd_context.option_enable(cmd, opt_verbose)); + return report_reference(file_name.c_str(), module_name, + openfpga_ctx.module_graph(), + !cmd_context.option_enable(cmd, opt_no_time_stamp), + cmd_context.option_enable(cmd, opt_verbose)); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 3f66c9ebe..74494934c 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -935,16 +935,16 @@ ShellCommandId add_report_reference_command_template( const std::vector& dependent_cmds, const bool& hidden) { Command shell_cmd("report_reference"); /* Add an option '--file' in short '-f'*/ - CommandOptionId opt_file = shell_cmd.add_option( - "file", true, - "specify the file to output results"); + CommandOptionId opt_file = + shell_cmd.add_option("file", true, "specify the file to output results"); shell_cmd.set_option_short_name(opt_file, "f"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); /* Add an option '--module'*/ - CommandOptionId opt_module = shell_cmd.add_option( - "module", false, - "specify the module under which the references of child modules will be reported"); + CommandOptionId opt_module = + shell_cmd.add_option("module", false, + "specify the module under which the references of " + "child modules will be reported"); shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING); /* Add an option '--no_time_stamp' */ @@ -954,13 +954,14 @@ ShellCommandId add_report_reference_command_template( shell_cmd.add_option("verbose", false, "Show verbose outputs"); /* Add command to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, - "report the number of instances for each unique module, under a given module", - hidden); + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, + "report the number of instances for each unique module, " + "under a given module", + hidden); shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_const_execute_function( - shell_cmd_id, report_reference_template); + shell.set_command_const_execute_function(shell_cmd_id, + report_reference_template); /* Add command dependency to the Shell */ shell.set_command_dependency(shell_cmd_id, dependent_cmds); @@ -1225,11 +1226,9 @@ void add_setup_command_templates(openfpga::Shell& shell, */ /* The command should NOT be executed before 'build_fabric' */ std::vector cmd_dependency_report_reference; - cmd_dependency_report_reference.push_back( - build_fabric_cmd_id); + cmd_dependency_report_reference.push_back(build_fabric_cmd_id); add_report_reference_command_template( - shell, openfpga_setup_cmd_class, - cmd_dependency_report_reference, hidden); + shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden); } } /* end namespace openfpga */ diff --git a/openfpga/src/utils/report_reference.cpp b/openfpga/src/utils/report_reference.cpp index e7e0cf9b7..169349dc6 100644 --- a/openfpga/src/utils/report_reference.cpp +++ b/openfpga/src/utils/report_reference.cpp @@ -5,8 +5,8 @@ #include #include #include -#include #include +#include /* Headers from vtrutil library */ #include "vtr_assert.h" @@ -16,7 +16,6 @@ /* Headers from openfpgautil library */ #include "command_exit_codes.h" #include "openfpga_digest.h" - #include "report_reference.h" /* begin namespace openfpga */ @@ -25,11 +24,9 @@ namespace openfpga { /******************************************************************** * Top-level function *******************************************************************/ -int report_reference(const char* fname, - const std::string& module_name, +int report_reference(const char* fname, const std::string& module_name, const ModuleManager& module_manager, - const bool& include_time_stamp, - const bool& verbose) { + const bool& include_time_stamp, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Report reference"); std::fstream fp; @@ -43,43 +40,58 @@ int report_reference(const char* fname, } ModuleId parent_module = module_manager.find_module(module_name); - if (ModuleId::INVALID() == parent_module){ + if (ModuleId::INVALID() == parent_module) { VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str()); return CMD_EXEC_MINOR_ERROR; } - if (module_manager.child_modules(parent_module).size() < 1){ + if (module_manager.child_modules(parent_module).size() < 1) { VTR_LOG_ERROR("Module %s hasn't any child module\n", module_name.c_str()); return CMD_EXEC_MINOR_ERROR; } - VTR_LOG("------------------------------------------------------------------------------\n"); - VTR_LOG("Module Reference count\n"); - VTR_LOG("------------------------------------------------------------------------------\n"); + VTR_LOG( + "--------------------------------------------------------------------------" + "----\n"); + VTR_LOG( + "Module Reference " + "count\n"); + VTR_LOG( + "--------------------------------------------------------------------------" + "----\n"); size_t ref_cnt = 0; - for (ModuleId child_module : module_manager.child_modules(parent_module)){ + for (ModuleId child_module : module_manager.child_modules(parent_module)) { std::string child_module_name = module_manager.module_name(child_module); - std::vector child_inst_vec = module_manager.child_module_instances(parent_module, child_module); - for (size_t pos = 0; pos < child_module_name.length(); pos += 70){ + std::vector child_inst_vec = + module_manager.child_module_instances(parent_module, child_module); + for (size_t pos = 0; pos < child_module_name.length(); pos += 70) { if (pos > 0) VTR_LOG("\n"); VTR_LOG("%-70s", child_module_name.substr(pos).c_str()); } VTR_LOG(" %7d\n", child_inst_vec.size()); ref_cnt += child_inst_vec.size(); } - VTR_LOG("------------------------------------------------------------------------------\n"); - VTR_LOG("Total %zu modules %zu references\n", module_manager.child_modules(parent_module).size(), ref_cnt); - VTR_LOG("------------------------------------------------------------------------------\n"); + VTR_LOG( + "--------------------------------------------------------------------------" + "----\n"); + VTR_LOG("Total %zu modules %zu references\n", + module_manager.child_modules(parent_module).size(), ref_cnt); + VTR_LOG( + "--------------------------------------------------------------------------" + "----\n"); fp << "references:" << std::endl; - for (ModuleId child_module : module_manager.child_modules(parent_module)){ + for (ModuleId child_module : module_manager.child_modules(parent_module)) { std::string child_module_name = module_manager.module_name(child_module); - std::vector child_inst_vec = module_manager.child_module_instances(parent_module, child_module); + std::vector child_inst_vec = + module_manager.child_module_instances(parent_module, child_module); fp << "- module: " << child_module_name.c_str() << "\n" << " reference count: " << child_inst_vec.size() << "\n" - << " instances:" << "\n"; - for (size_t inst_id : child_inst_vec){ - std::string inst_name = module_manager.instance_name(parent_module, child_module, inst_id); + << " instances:" + << "\n"; + for (size_t inst_id : child_inst_vec) { + std::string inst_name = + module_manager.instance_name(parent_module, child_module, inst_id); fp << " - " << inst_name.c_str() << "\n"; } } diff --git a/openfpga/src/utils/report_reference.h b/openfpga/src/utils/report_reference.h index 6bed89b90..c33559204 100644 --- a/openfpga/src/utils/report_reference.h +++ b/openfpga/src/utils/report_reference.h @@ -14,11 +14,9 @@ /* begin namespace openfpga */ namespace openfpga { -int report_reference(const char* fname, - const std::string& module_name, +int report_reference(const char* fname, const std::string& module_name, const ModuleManager& module_manager, - const bool& include_time_stamp, - const bool& verbose); + const bool& include_time_stamp, const bool& verbose); } /* end namespace openfpga */ #endif From 4aca4fda6f6b3c66983547ed01cdcf5d1dfef483 Mon Sep 17 00:00:00 2001 From: Victor Date: Thu, 5 Sep 2024 10:43:53 +0800 Subject: [PATCH 03/20] fix issue in reg test --- .../src/base/openfpga_setup_command_template.h | 12 ++++++++---- openfpga/src/utils/report_reference.cpp | 15 ++++++++------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 74494934c..d0729cb36 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -710,6 +710,12 @@ ShellCommandId add_route_clock_rr_graph_command_template( shell_cmd.set_option_short_name(opt_file, "pcf"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); + shell_cmd.add_option("disable_unused_trees", false, + "Disable entire clock trees when they are not used by " + "any clock nets. Useful to reduce clock power"); + shell_cmd.add_option("disable_unused_spines", false, + "Disable part of the clock tree which are used by clock " + "nets. Useful to reduce clock power"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); @@ -949,14 +955,14 @@ ShellCommandId add_report_reference_command_template( /* Add an option '--no_time_stamp' */ shell_cmd.add_option("no_time_stamp", false, - "Do not print time stamp in output files"); + "do not print time stamp in output files"); shell_cmd.add_option("verbose", false, "Show verbose outputs"); /* Add command to the Shell */ ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, - "report the number of instances for each unique module, " + "report all instances of each unique module, " "under a given module", hidden); shell.set_command_class(shell_cmd_id, cmd_class_id); @@ -1224,9 +1230,7 @@ void add_setup_command_templates(openfpga::Shell& shell, /******************************** * Command 'report_reference' */ - /* The command should NOT be executed before 'build_fabric' */ std::vector cmd_dependency_report_reference; - cmd_dependency_report_reference.push_back(build_fabric_cmd_id); add_report_reference_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden); } diff --git a/openfpga/src/utils/report_reference.cpp b/openfpga/src/utils/report_reference.cpp index 169349dc6..19d623aae 100644 --- a/openfpga/src/utils/report_reference.cpp +++ b/openfpga/src/utils/report_reference.cpp @@ -46,7 +46,7 @@ int report_reference(const char* fname, const std::string& module_name, } if (module_manager.child_modules(parent_module).size() < 1) { - VTR_LOG_ERROR("Module %s hasn't any child module\n", module_name.c_str()); + VTR_LOG_ERROR("Module %s contains no child module\n", module_name.c_str()); return CMD_EXEC_MINOR_ERROR; } @@ -64,11 +64,7 @@ int report_reference(const char* fname, const std::string& module_name, std::string child_module_name = module_manager.module_name(child_module); std::vector child_inst_vec = module_manager.child_module_instances(parent_module, child_module); - for (size_t pos = 0; pos < child_module_name.length(); pos += 70) { - if (pos > 0) VTR_LOG("\n"); - VTR_LOG("%-70s", child_module_name.substr(pos).c_str()); - } - VTR_LOG(" %7d\n", child_inst_vec.size()); + VTR_LOG("%-s %d\n", child_module_name.c_str(), child_inst_vec.size()); ref_cnt += child_inst_vec.size(); } VTR_LOG( @@ -80,6 +76,11 @@ int report_reference(const char* fname, const std::string& module_name, "--------------------------------------------------------------------------" "----\n"); + if (verbose) { + fp << "\nTotal " << module_manager.child_modules(parent_module).size() + << " modules " << ref_cnt << " references\n"; + } + fp << "references:" << std::endl; for (ModuleId child_module : module_manager.child_modules(parent_module)) { std::string child_module_name = module_manager.module_name(child_module); @@ -92,7 +93,7 @@ int report_reference(const char* fname, const std::string& module_name, for (size_t inst_id : child_inst_vec) { std::string inst_name = module_manager.instance_name(parent_module, child_module, inst_id); - fp << " - " << inst_name.c_str() << "\n"; + if (inst_name.size() > 0) fp << " - " << inst_name.c_str() << "\n"; } } From 7919e455f0111d84d8f9108fb848559dfbd36cf5 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri, 6 Sep 2024 06:32:59 +0000 Subject: [PATCH 04/20] Bump yosys from `0fc5812` to `e8951ab` Bumps [yosys](https://github.com/YosysHQ/yosys) from `0fc5812` to `e8951ab`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/0fc5812dcd0c62830f4faa27c4b62c03f3fd91ad...e8951aba29faf774e475f20c1405162993235d7f) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 0fc5812dc..e8951aba2 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 0fc5812dcd0c62830f4faa27c4b62c03f3fd91ad +Subproject commit e8951aba29faf774e475f20c1405162993235d7f From 7bacc781d04ff98d3528ea635c006c34b6a81d7b Mon Sep 17 00:00:00 2001 From: Victor Date: Fri, 6 Sep 2024 15:27:00 +0800 Subject: [PATCH 05/20] update code according to code review comments --- .../openfpga_commands/setup_commands.rst | 23 +++ .../base/openfpga_setup_command_template.h | 3 + openfpga/src/utils/report_reference.cpp | 150 ++++++++++++------ openfpga/src/utils/report_reference.h | 11 ++ .../report_reference_example_script.openfpga | 35 ++++ .../report_reference/config/task.conf | 34 ++++ 6 files changed, 210 insertions(+), 46 deletions(-) create mode 100644 openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga create mode 100644 openfpga_flow/tasks/basic_tests/report_reference/config/task.conf diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index ab27eeceb..dc20b75a4 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -521,3 +521,26 @@ write_fabric_pin_physical_location .. option:: --verbose Show verbose log + +.. _openfpga_setup_commands_report_reference: + +report_reference +~~~~~~~~~~~~~~~~~~~~ + + Write reference information of each child module under a given parent module to a YAML file + + .. option:: --file or -f + + Specify the file name to write the reference information + + .. option:: --module + + Specify the parent module name, under which the references of each child module will be reported. + + .. option:: --no_time_stamp + + Do not print time stamp in output files + + .. option:: --verbose + + Show verbose info \ No newline at end of file diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index d0729cb36..91b73acc3 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -1230,7 +1230,10 @@ void add_setup_command_templates(openfpga::Shell& shell, /******************************** * Command 'report_reference' */ + /* The command should NOT be executed before 'build_fabric' */ std::vector cmd_dependency_report_reference; + cmd_dependency_write_fabric_pin_physical_location.push_back( + build_fabric_cmd_id); add_report_reference_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden); } diff --git a/openfpga/src/utils/report_reference.cpp b/openfpga/src/utils/report_reference.cpp index 19d623aae..9599c5b0a 100644 --- a/openfpga/src/utils/report_reference.cpp +++ b/openfpga/src/utils/report_reference.cpp @@ -16,6 +16,7 @@ /* Headers from openfpgautil library */ #include "command_exit_codes.h" #include "openfpga_digest.h" +#include "openfpga_naming.h" #include "report_reference.h" /* begin namespace openfpga */ @@ -29,6 +30,54 @@ int report_reference(const char* fname, const std::string& module_name, const bool& include_time_stamp, const bool& verbose) { vtr::ScopedStartFinishTimer timer("Report reference"); + ModuleId parent_module = module_manager.find_module(module_name); + if (false == module_manager.valid_module_id(parent_module)) { + VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str()); + + if (verbose) write_module_to_file(fname, module_manager); + return CMD_EXEC_FATAL_ERROR; + } + + show_reference_count(parent_module, module_manager); + + return write_reference_to_file(fname, parent_module, module_manager, + include_time_stamp, verbose); +} + +/******************************************************************** + * show reference count of each child module under given parent module + *******************************************************************/ +void show_reference_count(const ModuleId& parent_module, + const ModuleManager& module_manager) { + VTR_LOG( + "----------------------------------------------------------------------\n"); + VTR_LOG( + "Module Count \n"); + VTR_LOG( + "--------------------------------------------------------------------- \n"); + size_t ref_cnt = 0; + for (ModuleId child_module : module_manager.child_modules(parent_module)) { + std::string child_module_name = module_manager.module_name(child_module); + std::vector child_inst_vec = + module_manager.child_module_instances(parent_module, child_module); + VTR_LOG("%-s %d\n", child_module_name.c_str(), child_inst_vec.size()); + ref_cnt += child_inst_vec.size(); + } + VTR_LOG( + "----------------------------------------------------------------------\n"); + VTR_LOG("Total: %zu modules %zu references\n", + module_manager.child_modules(parent_module).size(), ref_cnt); + VTR_LOG( + "----------------------------------------------------------------------\n"); +} + +/******************************************************************** + * write reference info to a given file in YAML format + *******************************************************************/ +int write_reference_to_file(const char* fname, const ModuleId& parent_module, + const ModuleManager& module_manager, + const bool& include_time_stamp, + const bool& verbose) { std::fstream fp; fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); openfpga::check_file_stream(fname, fp); @@ -39,67 +88,76 @@ int report_reference(const char* fname, const std::string& module_name, fp << "Date: " << std::ctime(&end_time) << std::endl; } - ModuleId parent_module = module_manager.find_module(module_name); - if (ModuleId::INVALID() == parent_module) { - VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str()); - return CMD_EXEC_MINOR_ERROR; - } + fp << "#the instance names are given during netlist generation" << std::endl; - if (module_manager.child_modules(parent_module).size() < 1) { - VTR_LOG_ERROR("Module %s contains no child module\n", module_name.c_str()); - return CMD_EXEC_MINOR_ERROR; - } - - VTR_LOG( - "--------------------------------------------------------------------------" - "----\n"); - VTR_LOG( - "Module Reference " - "count\n"); - VTR_LOG( - "--------------------------------------------------------------------------" - "----\n"); size_t ref_cnt = 0; - for (ModuleId child_module : module_manager.child_modules(parent_module)) { - std::string child_module_name = module_manager.module_name(child_module); - std::vector child_inst_vec = - module_manager.child_module_instances(parent_module, child_module); - VTR_LOG("%-s %d\n", child_module_name.c_str(), child_inst_vec.size()); - ref_cnt += child_inst_vec.size(); - } - VTR_LOG( - "--------------------------------------------------------------------------" - "----\n"); - VTR_LOG("Total %zu modules %zu references\n", - module_manager.child_modules(parent_module).size(), ref_cnt); - VTR_LOG( - "--------------------------------------------------------------------------" - "----\n"); - - if (verbose) { - fp << "\nTotal " << module_manager.child_modules(parent_module).size() - << " modules " << ref_cnt << " references\n"; - } - fp << "references:" << std::endl; for (ModuleId child_module : module_manager.child_modules(parent_module)) { std::string child_module_name = module_manager.module_name(child_module); std::vector child_inst_vec = module_manager.child_module_instances(parent_module, child_module); - fp << "- module: " << child_module_name.c_str() << "\n" - << " reference count: " << child_inst_vec.size() << "\n" - << " instances:" - << "\n"; + fp << "- module: " << child_module_name.c_str() << std::endl + << " count: " << child_inst_vec.size() << std::endl + << " instances:" << std::endl; for (size_t inst_id : child_inst_vec) { std::string inst_name = module_manager.instance_name(parent_module, child_module, inst_id); - if (inst_name.size() > 0) fp << " - " << inst_name.c_str() << "\n"; + fp << " - "; + if (true == inst_name.empty()) { + fp << generate_instance_name(child_module_name, inst_id) << std::endl; + } else { + fp << inst_name << std::endl; + } } + ref_cnt += child_inst_vec.size(); + } + + if (verbose) { + fp << std::endl + << "Total: " << module_manager.child_modules(parent_module).size() + << " modules " << ref_cnt << " references" << std::endl; } fp.close(); - return CMD_EXEC_SUCCESS; } +/******************************************************************** + * write all modules to a given file + *******************************************************************/ +void write_module_to_file(const char* fname, + const ModuleManager& module_manager) { + std::fstream fp; + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + openfpga::check_file_stream(fname, fp); + + fp << "module_count: " << module_manager.modules().size() << std::endl; + + for (ModuleId curr_module : module_manager.modules()) { + std::string curr_module_name = module_manager.module_name(curr_module); + fp << "module: " << curr_module_name.c_str() << std::endl; + + for (ModuleId child_module : module_manager.child_modules(curr_module)) { + std::string child_module_name = module_manager.module_name(child_module); + std::vector child_inst_vec = + module_manager.child_module_instances(curr_module, child_module); + fp << " - child_module:" << child_module_name.c_str() << std::endl + << " instance_count:" << child_inst_vec.size() << std::endl + << " instances:" << std::endl; + + for (size_t inst_id : child_inst_vec) { + std::string inst_name = + module_manager.instance_name(curr_module, child_module, inst_id); + fp << " - "; + if (true == inst_name.empty()) { + fp << generate_instance_name(child_module_name, inst_id) << std::endl; + } else { + fp << inst_name << std::endl; + } + } + } + } + fp.close(); +} + } /* end namespace openfpga */ diff --git a/openfpga/src/utils/report_reference.h b/openfpga/src/utils/report_reference.h index c33559204..ac74d01c3 100644 --- a/openfpga/src/utils/report_reference.h +++ b/openfpga/src/utils/report_reference.h @@ -17,6 +17,17 @@ namespace openfpga { int report_reference(const char* fname, const std::string& module_name, const ModuleManager& module_manager, const bool& include_time_stamp, const bool& verbose); + +void show_reference_count(const ModuleId& parent_module, + const ModuleManager& module_manager); + +int write_reference_to_file(const char* fname, const ModuleId& parent_module, + const ModuleManager& module_manager, + const bool& include_time_stamp, + const bool& verbose); + +void write_module_to_file(const char* fname, + const ModuleManager& module_manager); } /* end namespace openfpga */ #endif diff --git a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga new file mode 100644 index 000000000..635efae58 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga @@ -0,0 +1,35 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enabled frame view creation to save runtime and memory +# Note that this is turned on when bitstream generation +# is the ONLY purpose of the flow!!! +build_fabric --compress_routing --frame_view #--verbose + +# Report reference to a file +report_reference ${OPENFPGA_REPORT_REFERENCE_OPTIONS} + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf b/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf new file mode 100644 index 000000000..4f40f2eb2 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_report_reference_options=--file reference_info.yaml --module grid_io_right + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] From 9a2fc86dcdb70df4c2e55f832ec7e6297ed61310 Mon Sep 17 00:00:00 2001 From: Victor Date: Fri, 6 Sep 2024 17:58:47 +0800 Subject: [PATCH 06/20] add dependency on build_fabric --- openfpga/src/base/openfpga_setup_command_template.h | 3 +-- .../report_reference_example_script.openfpga | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 91b73acc3..5dbd12f6f 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -1232,8 +1232,7 @@ void add_setup_command_templates(openfpga::Shell& shell, */ /* The command should NOT be executed before 'build_fabric' */ std::vector cmd_dependency_report_reference; - cmd_dependency_write_fabric_pin_physical_location.push_back( - build_fabric_cmd_id); + cmd_dependency_report_reference.push_back(build_fabric_cmd_id); add_report_reference_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden); } diff --git a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga index 635efae58..f24476e91 100644 --- a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga @@ -23,7 +23,7 @@ lut_truth_table_fixup # - Enabled frame view creation to save runtime and memory # Note that this is turned on when bitstream generation # is the ONLY purpose of the flow!!! -build_fabric --compress_routing --frame_view #--verbose +#build_fabric --compress_routing --frame_view #--verbose # Report reference to a file report_reference ${OPENFPGA_REPORT_REFERENCE_OPTIONS} From 83fc1210b5f2d8883260e694998ea67be7d0e4f3 Mon Sep 17 00:00:00 2001 From: Victor Date: Fri, 6 Sep 2024 18:28:23 +0800 Subject: [PATCH 07/20] add test case of report_reference to basic_reg_test.sh --- .../report_reference_example_script.openfpga | 2 +- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga index f24476e91..635efae58 100644 --- a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga @@ -23,7 +23,7 @@ lut_truth_table_fixup # - Enabled frame view creation to save runtime and memory # Note that this is turned on when bitstream generation # is the ONLY purpose of the flow!!! -#build_fabric --compress_routing --frame_view #--verbose +build_fabric --compress_routing --frame_view #--verbose # Report reference to a file report_reference ${OPENFPGA_REPORT_REFERENCE_OPTIONS} diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index b968904fb..922e399b4 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -314,6 +314,10 @@ run-task basic_tests/no_time_stamp/device_1x1 $@ run-task basic_tests/no_time_stamp/device_4x4 $@ run-task basic_tests/no_time_stamp/no_cout_in_gsb $@ run-task basic_tests/no_time_stamp/dump_waveform $@ + +echo -e "Testing report reference to file"; +run-task basic_tests/report_reference $@ + # Run git-diff to ensure no changes on the golden netlists # Switch to root path in case users are running the tests in another location cd ${OPENFPGA_PATH} From f7aaead5134d506427c5896085056deeccd28fe6 Mon Sep 17 00:00:00 2001 From: rafljiarui Date: Fri, 6 Sep 2024 13:14:59 -0500 Subject: [PATCH 08/20] Fixed typo in vpr-main.cpp --- openfpga/src/vpr_wrapper/vpr_main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/vpr_wrapper/vpr_main.cpp b/openfpga/src/vpr_wrapper/vpr_main.cpp index 940fc0644..c872a17a4 100644 --- a/openfpga/src/vpr_wrapper/vpr_main.cpp +++ b/openfpga/src/vpr_wrapper/vpr_main.cpp @@ -68,7 +68,7 @@ static int vpr(int argc, char** argv) { */ /* vpr_free_all(Arch, vpr_setup); */ - VTR_LOG("VPR suceeded\n"); + VTR_LOG("VPR succeeded\n"); } catch (const tatum::Error& tatum_error) { VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str()); From 8d97ebd98015e64987b6709259f77d9602e1fca6 Mon Sep 17 00:00:00 2001 From: Victor Date: Mon, 9 Sep 2024 17:49:10 +0800 Subject: [PATCH 09/20] Add more test cases and update documentation about the YAML file format of this command --- .../manual/file_formats/reference_file.rst | 80 +++++++++++++++++++ .../report_reference_example_script.openfpga | 4 +- .../report_reference/config/task.conf | 4 +- 3 files changed, 86 insertions(+), 2 deletions(-) create mode 100644 docs/source/manual/file_formats/reference_file.rst diff --git a/docs/source/manual/file_formats/reference_file.rst b/docs/source/manual/file_formats/reference_file.rst new file mode 100644 index 000000000..f2240df62 --- /dev/null +++ b/docs/source/manual/file_formats/reference_file.rst @@ -0,0 +1,80 @@ +.. _file_format_reference_file: + +Reference File (.yaml) +---------------------------------------- + +This file is generated by command :ref:`openfpga_setup_commands_report_reference` + + +The reference file aims to the show reference number of each child module of given parent module + +By using the options of the command :ref:`openfpga_setup_commands_report_reference`, user can selectively output the reference info under the given parent module on their needs. + +An example of the file is shown as follows. + +.. code-block:: yaml + +Date: Mon Sep 9 16:41:53 2024 + +#the instance names are given during netlist generation +references: +- module: grid_io_top + count: 1 + instances: + - grid_io_top_1__2_ +- module: grid_io_right + count: 1 + instances: + - grid_io_right_2__1_ +- module: grid_io_bottom + count: 1 + instances: + - grid_io_bottom_1__0_ +- module: grid_io_left + count: 1 + instances: + - grid_io_left_0__1_ +- module: grid_clb + count: 1 + instances: + - grid_clb_1__1_ +- module: sb_0__0_ + count: 1 + instances: + - sb_0__0_ +- module: sb_0__1_ + count: 1 + instances: + - sb_0__1_ +- module: sb_1__0_ + count: 1 + instances: + - sb_1__0_ +- module: sb_1__1_ + count: 1 + instances: + - sb_1__1_ +- module: cbx_1__0_ + count: 1 + instances: + - cbx_1__0_ +- module: cbx_1__1_ + count: 1 + instances: + - cbx_1__1_ +- module: cby_0__1_ + count: 1 + instances: + - cby_0__1_ +- module: cby_1__1_ + count: 1 + instances: + - cby_1__1_ + direct_interc + +In this example, the parent module is ``fpga_top``. +The child modules under ``fpga_top`` are ``grid_io_top``, ``grid_io_right``, and etc. + +The instance of the child module ``grid_io_top`` is shown as a list as below: + - grid_io_top_1__2_ + diff --git a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga index 635efae58..f7e4d4f10 100644 --- a/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga @@ -26,7 +26,9 @@ lut_truth_table_fixup build_fabric --compress_routing --frame_view #--verbose # Report reference to a file -report_reference ${OPENFPGA_REPORT_REFERENCE_OPTIONS} +report_reference ${OPENFPGA_REPORT_REFERENCE_MODULE_OPTIONS} +report_reference ${OPENFPGA_REPORT_REFERENCE_VERBOSE_OPTIONS} +report_reference ${OPENFPGA_REPORT_REFERENCE_NO_TIME_STAMP_OPTIONS} # Finish and exit OpenFPGA exit diff --git a/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf b/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf index 4f40f2eb2..0fa9feefd 100644 --- a/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/report_reference/config/task.conf @@ -19,7 +19,9 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -openfpga_report_reference_options=--file reference_info.yaml --module grid_io_right +openfpga_report_reference_module_options=--file reference_module.yaml --module fpga_top +openfpga_report_reference_verbose_options=--file reference_verbose.yaml --module fpga_top --verbose +openfpga_report_reference_no_time_stamp_options=--file reference_no_time_stamp.yaml --module grid_io_right --no_time_stamp [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml From c9f06c6d64fded783450483c2dbb55a861a5bea8 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 9 Sep 2024 17:27:10 +0000 Subject: [PATCH 10/20] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 726c3b05d..048533197 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2710 +1.2.2717 From 5f50e4623c13271d80aa9f936014fd59c8afbd11 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 Sep 2024 12:21:09 -0700 Subject: [PATCH 11/20] [core] add a new option map_global_net_to_msb for pb_pin_fixup --- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 22 ++++++++++++++----- openfpga/src/base/openfpga_pb_pin_fixup.h | 1 + .../src/base/openfpga_pb_pin_fixup_template.h | 2 ++ .../base/openfpga_setup_command_template.h | 2 ++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 3ae0cc8e2..ab32ecc43 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -32,7 +32,9 @@ namespace openfpga { static int update_cluster_pin_global_net_with_post_routing_results( const ClusteringContext& clustering_ctx, VprClusteringAnnotation& clustering_annotation, const ClusterBlockId& blk_id, - t_logical_block_type_ptr logical_block, size_t& num_fixup, + t_logical_block_type_ptr logical_block, + const bool& map_gnet2msb, + size_t& num_fixup, const bool& verbose) { /* Reassign global nets to unused pins in the same port where they were mapped * NO optimization is done here!!! First find first fit @@ -78,9 +80,13 @@ static int update_cluster_pin_global_net_with_post_routing_results( clustering_ctx.clb_nlist.net_name(global_net_id).c_str()); size_t cand_pin_start = pb_type_pin - pb_graph_pin->pin_number; size_t cand_pin_end = cand_pin_start + pb_graph_pin->port->num_pins; + std::vector cand_pins(pb_graph_pin->port->num_pins); + std::itoa(cand_pins.begin(), cand_pins.end(), cand_pin_start); + if (map_gnet2msb) { + std::reverse(cand_pins.begin(), cand_pins.end()); + } bool found_cand = false; - for (size_t cand_pin = cand_pin_start; cand_pin < cand_pin_end; - ++cand_pin) { + for (size_t cand_pin : cand_pins) { ClusterNetId cand_pin_net_id = clustering_ctx.clb_nlist.block_net(blk_id, cand_pin); const t_pb_graph_pin* cand_pb_graph_pin = @@ -139,6 +145,7 @@ static int update_cluster_pin_with_post_routing_results( VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer, const vtr::Point& grid_coord, const ClusterBlockId& blk_id, const e_side& border_side, const size_t& z, const bool& perimeter_cb, + const bool& map_gnet2msb, size_t& num_fixup, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Handle each pin */ @@ -337,7 +344,7 @@ static int update_cluster_pin_with_post_routing_results( } /* 2nd round of fixup: focus on global nets */ status = update_cluster_pin_global_net_with_post_routing_results( - clustering_ctx, vpr_clustering_annotation, blk_id, logical_block, num_fixup, + clustering_ctx, vpr_clustering_annotation, blk_id, logical_block, map_gnet2msb, num_fixup, verbose); return status; } @@ -351,9 +358,12 @@ int update_pb_pin_with_post_routing_results( const PlacementContext& placement_ctx, const VprRoutingAnnotation& vpr_routing_annotation, VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb, + const bool& map_gnet2msb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; size_t num_fixup = 0; + /* Confirm options */ + VTR_LOGV(verbose && map_gnet2msb, "User choose to map global net to the best fit MSB of input port\n") /* Ensure a clean start: remove all the remapping results from VTR's * post-routing clustering result sync-up */ vpr_clustering_annotation.clear_net_remapping(); @@ -384,7 +394,7 @@ int update_pb_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, vpr_clustering_annotation, layer, grid_coord, cluster_blk_id, NUM_SIDES, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, - perimeter_cb, num_fixup, verbose); + perimeter_cb, map_gnet2msb, num_fixup, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -419,7 +429,7 @@ int update_pb_pin_with_post_routing_results( device_ctx, clustering_ctx, vpr_routing_annotation, vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, perimeter_cb, - num_fixup, verbose); + map_gnet2msb, num_fixup, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.h b/openfpga/src/base/openfpga_pb_pin_fixup.h index 11813b60c..621157ae4 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.h +++ b/openfpga/src/base/openfpga_pb_pin_fixup.h @@ -19,6 +19,7 @@ int update_pb_pin_with_post_routing_results( const PlacementContext& placement_ctx, const VprRoutingAnnotation& vpr_routing_annotation, VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb, + const bool& map_gnet2msb, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_pb_pin_fixup_template.h b/openfpga/src/base/openfpga_pb_pin_fixup_template.h index 50c415727..beb402572 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup_template.h +++ b/openfpga/src/base/openfpga_pb_pin_fixup_template.h @@ -35,6 +35,7 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd, vtr::ScopedStartFinishTimer timer( "Fix up pb pin mapping results after routing optimization"); + CommandOptionId opt_map_gnet2msb = cmd.option("map_global_net_to_msb"); CommandOptionId opt_verbose = cmd.option("verbose"); /* Apply fix-up to each grid */ @@ -43,6 +44,7 @@ int pb_pin_fixup_template(T& openfpga_context, const Command& cmd, openfpga_context.vpr_routing_annotation(), openfpga_context.mutable_vpr_clustering_annotation(), g_vpr_ctx.device().arch->perimeter_cb, + cmd_context.option_enable(cmd, opt_map_gnet2msb), cmd_context.option_enable(cmd, opt_verbose)); } diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 53e43f00f..5d8af4205 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -324,6 +324,8 @@ ShellCommandId add_pb_pin_fixup_command_template( const std::vector& dependent_cmds, const bool& hidden) { Command shell_cmd("pb_pin_fixup"); + /* Add an option '--map_global_net_to_msb' */ + shell_cmd.add_option("map_global_net_to_msb", false, "If specified, any global net including clock, reset etc, will be mapped to a best-fit Most Significant Bit (MSB) of input ports of programmable blocks. If not specified, a best-fit Least Significant Bit (LSB) will be the default choice"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); From fc92ecea245032f6e6c5cd6b044556f3bdcefac9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 Sep 2024 12:43:38 -0700 Subject: [PATCH 12/20] [core] typo --- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index ab32ecc43..1d46f0c48 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -81,7 +81,7 @@ static int update_cluster_pin_global_net_with_post_routing_results( size_t cand_pin_start = pb_type_pin - pb_graph_pin->pin_number; size_t cand_pin_end = cand_pin_start + pb_graph_pin->port->num_pins; std::vector cand_pins(pb_graph_pin->port->num_pins); - std::itoa(cand_pins.begin(), cand_pins.end(), cand_pin_start); + std::iota(cand_pins.begin(), cand_pins.end(), cand_pin_start); if (map_gnet2msb) { std::reverse(cand_pins.begin(), cand_pins.end()); } From e3b99e88ff75e3b7a0018a16dcb1e856d23221b8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 Sep 2024 12:46:23 -0700 Subject: [PATCH 13/20] [core] syntax --- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 1d46f0c48..9493a8cfd 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -79,7 +79,6 @@ static int update_cluster_pin_global_net_with_post_routing_results( "during routing optimization\n", clustering_ctx.clb_nlist.net_name(global_net_id).c_str()); size_t cand_pin_start = pb_type_pin - pb_graph_pin->pin_number; - size_t cand_pin_end = cand_pin_start + pb_graph_pin->port->num_pins; std::vector cand_pins(pb_graph_pin->port->num_pins); std::iota(cand_pins.begin(), cand_pins.end(), cand_pin_start); if (map_gnet2msb) { @@ -363,7 +362,7 @@ int update_pb_pin_with_post_routing_results( int status = CMD_EXEC_SUCCESS; size_t num_fixup = 0; /* Confirm options */ - VTR_LOGV(verbose && map_gnet2msb, "User choose to map global net to the best fit MSB of input port\n") + VTR_LOGV(verbose && map_gnet2msb, "User choose to map global net to the best fit MSB of input port\n"); /* Ensure a clean start: remove all the remapping results from VTR's * post-routing clustering result sync-up */ vpr_clustering_annotation.clear_net_remapping(); From 7250a7d70349d173e42752225f33fabac08a3217 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 Sep 2024 12:46:46 -0700 Subject: [PATCH 14/20] [core] code format --- openfpga/src/base/openfpga_pb_pin_fixup.cpp | 19 ++++++++----------- openfpga/src/base/openfpga_pb_pin_fixup.h | 3 +-- .../base/openfpga_setup_command_template.h | 7 ++++++- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp index 9493a8cfd..79c73e327 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp +++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp @@ -32,10 +32,8 @@ namespace openfpga { static int update_cluster_pin_global_net_with_post_routing_results( const ClusteringContext& clustering_ctx, VprClusteringAnnotation& clustering_annotation, const ClusterBlockId& blk_id, - t_logical_block_type_ptr logical_block, - const bool& map_gnet2msb, - size_t& num_fixup, - const bool& verbose) { + t_logical_block_type_ptr logical_block, const bool& map_gnet2msb, + size_t& num_fixup, const bool& verbose) { /* Reassign global nets to unused pins in the same port where they were mapped * NO optimization is done here!!! First find first fit */ @@ -144,8 +142,7 @@ static int update_cluster_pin_with_post_routing_results( VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer, const vtr::Point& grid_coord, const ClusterBlockId& blk_id, const e_side& border_side, const size_t& z, const bool& perimeter_cb, - const bool& map_gnet2msb, - size_t& num_fixup, const bool& verbose) { + const bool& map_gnet2msb, size_t& num_fixup, const bool& verbose) { int status = CMD_EXEC_SUCCESS; /* Handle each pin */ auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id); @@ -343,8 +340,8 @@ static int update_cluster_pin_with_post_routing_results( } /* 2nd round of fixup: focus on global nets */ status = update_cluster_pin_global_net_with_post_routing_results( - clustering_ctx, vpr_clustering_annotation, blk_id, logical_block, map_gnet2msb, num_fixup, - verbose); + clustering_ctx, vpr_clustering_annotation, blk_id, logical_block, + map_gnet2msb, num_fixup, verbose); return status; } @@ -357,12 +354,12 @@ int update_pb_pin_with_post_routing_results( const PlacementContext& placement_ctx, const VprRoutingAnnotation& vpr_routing_annotation, VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb, - const bool& map_gnet2msb, - const bool& verbose) { + const bool& map_gnet2msb, const bool& verbose) { int status = CMD_EXEC_SUCCESS; size_t num_fixup = 0; /* Confirm options */ - VTR_LOGV(verbose && map_gnet2msb, "User choose to map global net to the best fit MSB of input port\n"); + VTR_LOGV(verbose && map_gnet2msb, + "User choose to map global net to the best fit MSB of input port\n"); /* Ensure a clean start: remove all the remapping results from VTR's * post-routing clustering result sync-up */ vpr_clustering_annotation.clear_net_remapping(); diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.h b/openfpga/src/base/openfpga_pb_pin_fixup.h index 621157ae4..1d7faa83b 100644 --- a/openfpga/src/base/openfpga_pb_pin_fixup.h +++ b/openfpga/src/base/openfpga_pb_pin_fixup.h @@ -19,8 +19,7 @@ int update_pb_pin_with_post_routing_results( const PlacementContext& placement_ctx, const VprRoutingAnnotation& vpr_routing_annotation, VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb, - const bool& map_gnet2msb, - const bool& verbose); + const bool& map_gnet2msb, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 5d8af4205..1d74a61f0 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -325,7 +325,12 @@ ShellCommandId add_pb_pin_fixup_command_template( Command shell_cmd("pb_pin_fixup"); /* Add an option '--map_global_net_to_msb' */ - shell_cmd.add_option("map_global_net_to_msb", false, "If specified, any global net including clock, reset etc, will be mapped to a best-fit Most Significant Bit (MSB) of input ports of programmable blocks. If not specified, a best-fit Least Significant Bit (LSB) will be the default choice"); + shell_cmd.add_option( + "map_global_net_to_msb", false, + "If specified, any global net including clock, reset etc, will be mapped " + "to a best-fit Most Significant Bit (MSB) of input ports of programmable " + "blocks. If not specified, a best-fit Least Significant Bit (LSB) will be " + "the default choice"); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); From 3b1f51b9d9d964193b7ef648505a2fcda764ac52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 Sep 2024 13:46:58 -0700 Subject: [PATCH 15/20] [doc] add new options --- .../openfpga_shell/openfpga_commands/setup_commands.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index ab27eeceb..d5fce4b8f 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -235,6 +235,10 @@ pb_pin_fixup .. warning:: This feature has been integrated into VPR to provide accurate timing analysis results at post-routing stage. However, this command provides a light fix-up (not as thorough as the one in VPR) but bring more flexibility in support some architecture without local routing. Suggest to enable it when your architecture does not have local routing for *Look-Up Tables* (LUTs) but you want to enable logic equivalent for input pins of LUTs .. warning:: This command may be deprecated in future + + .. option:: --map_global_net_to_msb + + If specified, any global net including clock, reset etc, will be mapped to a best-fit Most Significant Bit (MSB) of input ports of programmable blocks. If not specified, a best-fit Least Significant Bit (LSB) will be the default choice. For example, when ``--clock_modeling ideal`` is selected when running VPR, global nets will not be routed and their pin mapping on programmable blocks may be revoked by other nets due to optimization. Therefore, this command will restore the pin mapping for the global nets and pick a spare pin on programmable blocks. This option is to set a preference when mapping the global nets to spare pins. .. option:: --verbose From f912af513b714379b89bc4a466b1a604d6565db2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 9 Sep 2024 13:54:20 -0700 Subject: [PATCH 16/20] [test] add a new testcase to validate mapping gnet to msb during pb_pin_fix --- ...lkntwk_pb_pin_fixup_no_ace_script.openfpga | 2 +- .../regression_test_scripts/basic_reg_test.sh | 1 + .../config/task.conf | 1 + .../config/clk_arch_1clk_1rst_2layer.xml | 34 +++++++++++ .../config/pin_constraints_clk.xml | 8 +++ .../config/pin_constraints_rst.xml | 8 +++ .../config/pin_constraints_rst_and_clk.xml | 8 +++ .../config/repack_pin_constraints.xml | 4 ++ .../config/task.conf | 57 +++++++++++++++++++ 9 files changed, 122 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga index f77fadd10..b5e326b27 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga @@ -22,7 +22,7 @@ append_clock_rr_graph # to debug use --verbose options link_openfpga_arch --sort_gsb_chan_node_in_edges -pb_pin_fixup --verbose +pb_pin_fixup ${OPENFPGA_PB_PIN_FIXUP_OPTIONS} # Route clock based on clock network definition route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index b968904fb..6b17c21c6 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -250,6 +250,7 @@ run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unus run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf index a03c48cb9..0dad873c1 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup/config/task.conf @@ -25,6 +25,7 @@ openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= +openfpga_pb_pin_fixup_options=--verbose [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml new file mode 100644 index 000000000..b91512914 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/clk_arch_1clk_1rst_2layer.xml @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml new file mode 100644 index 000000000..f0b871511 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml new file mode 100644 index 000000000..15df5148e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/pin_constraints_rst_and_clk.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf new file mode 100644 index 000000000..2549ab7dc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf @@ -0,0 +1,57 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_pb_pin_fixup_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= +openfpga_pb_pin_fixup_options=--map_global_net_to_msb --verbose + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_on_lut/clk_on_lut.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst.xml + +bench1_top = clk_on_lut +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml + +bench2_top = rst_and_clk_on_lut +bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 3ac94ad7d8383da4e93fff36f9aeb39a28e2d3ab Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Mon, 9 Sep 2024 23:38:57 +0000 Subject: [PATCH 17/20] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index 048533197..e804e9051 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2717 +1.2.2726 From 3ea830e1684acbce488f36758ac302d5986b7684 Mon Sep 17 00:00:00 2001 From: Victor Date: Tue, 10 Sep 2024 10:46:15 +0800 Subject: [PATCH 18/20] Add the reference_file to the index.rst --- docs/source/manual/file_formats/index.rst | 2 ++ openfpga/src/utils/report_reference.cpp | 40 ----------------------- openfpga/src/utils/report_reference.h | 3 -- 3 files changed, 2 insertions(+), 43 deletions(-) diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index e873286fd..340bb3d8a 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -45,3 +45,5 @@ OpenFPGA widely uses XML format for interchangeable files fabric_pin_physical_location_file fabric_hierarchy_file + + reference_file diff --git a/openfpga/src/utils/report_reference.cpp b/openfpga/src/utils/report_reference.cpp index 9599c5b0a..3a3bea935 100644 --- a/openfpga/src/utils/report_reference.cpp +++ b/openfpga/src/utils/report_reference.cpp @@ -33,8 +33,6 @@ int report_reference(const char* fname, const std::string& module_name, ModuleId parent_module = module_manager.find_module(module_name); if (false == module_manager.valid_module_id(parent_module)) { VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str()); - - if (verbose) write_module_to_file(fname, module_manager); return CMD_EXEC_FATAL_ERROR; } @@ -122,42 +120,4 @@ int write_reference_to_file(const char* fname, const ModuleId& parent_module, return CMD_EXEC_SUCCESS; } -/******************************************************************** - * write all modules to a given file - *******************************************************************/ -void write_module_to_file(const char* fname, - const ModuleManager& module_manager) { - std::fstream fp; - fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); - openfpga::check_file_stream(fname, fp); - - fp << "module_count: " << module_manager.modules().size() << std::endl; - - for (ModuleId curr_module : module_manager.modules()) { - std::string curr_module_name = module_manager.module_name(curr_module); - fp << "module: " << curr_module_name.c_str() << std::endl; - - for (ModuleId child_module : module_manager.child_modules(curr_module)) { - std::string child_module_name = module_manager.module_name(child_module); - std::vector child_inst_vec = - module_manager.child_module_instances(curr_module, child_module); - fp << " - child_module:" << child_module_name.c_str() << std::endl - << " instance_count:" << child_inst_vec.size() << std::endl - << " instances:" << std::endl; - - for (size_t inst_id : child_inst_vec) { - std::string inst_name = - module_manager.instance_name(curr_module, child_module, inst_id); - fp << " - "; - if (true == inst_name.empty()) { - fp << generate_instance_name(child_module_name, inst_id) << std::endl; - } else { - fp << inst_name << std::endl; - } - } - } - } - fp.close(); -} - } /* end namespace openfpga */ diff --git a/openfpga/src/utils/report_reference.h b/openfpga/src/utils/report_reference.h index ac74d01c3..2afd89cc0 100644 --- a/openfpga/src/utils/report_reference.h +++ b/openfpga/src/utils/report_reference.h @@ -25,9 +25,6 @@ int write_reference_to_file(const char* fname, const ModuleId& parent_module, const ModuleManager& module_manager, const bool& include_time_stamp, const bool& verbose); - -void write_module_to_file(const char* fname, - const ModuleManager& module_manager); } /* end namespace openfpga */ #endif From 2d88e15d6604867b8a32ce980c23000585433e06 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Tue, 10 Sep 2024 06:38:41 +0000 Subject: [PATCH 19/20] Bump yosys from `e8951ab` to `6937241` Bumps [yosys](https://github.com/YosysHQ/yosys) from `e8951ab` to `6937241`. - [Release notes](https://github.com/YosysHQ/yosys/releases) - [Commits](https://github.com/YosysHQ/yosys/compare/e8951aba29faf774e475f20c1405162993235d7f...693724101280384479e0a3d15647a58a5e445a50) --- updated-dependencies: - dependency-name: yosys dependency-type: direct:production ... Signed-off-by: dependabot[bot] --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index e8951aba2..693724101 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit e8951aba29faf774e475f20c1405162993235d7f +Subproject commit 693724101280384479e0a3d15647a58a5e445a50 From fa0c1eb426d9e2225e4cd734b1fc175bc137df83 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 10 Sep 2024 17:03:56 +0000 Subject: [PATCH 20/20] Updated Patch Count --- VERSION.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION.md b/VERSION.md index e804e9051..da2e38162 100644 --- a/VERSION.md +++ b/VERSION.md @@ -1 +1 @@ -1.2.2726 +1.2.2739