diff --git a/fpga_flow/configs/tutorial/tuto.conf b/fpga_flow/configs/tutorial/tuto.conf
index 85104383a..35a15f032 100644
--- a/fpga_flow/configs/tutorial/tuto.conf
+++ b/fpga_flow/configs/tutorial/tuto.conf
@@ -1,27 +1,27 @@
 # Standard Configuration Example
 [dir_path]
-script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
-benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC
-yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
-odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
-cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
-abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
-abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
-abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
-mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
-m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
-mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
-vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
-rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial
-ace_path = OPENFPGAPATHKEYWORD/ace2/ace
+script_base = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/scripts/
+benchmark_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC
+yosys_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys
+odin2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/odin2.exe
+cirkit_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/cirkit
+abc_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/yosys/yosys-abc
+abc_mccl_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc
+abc_with_bb_support_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/abc_with_bb_support/abc
+mpack1_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack1
+m2net_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/m2net
+mpack2_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/not_used_atm/mpack2
+vpr_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/vpr
+rpt_dir = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/results_tutorial
+ace_path = /research/ece/lnis/USERS/tang/github/OpenFPGA/ace2/ace
 
 [flow_conf]
 flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
-vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
+vpr_arch = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml
 mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
-m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
+m2net_conf = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf
 mpack2_arch = K6_pattern7_I24.arch
-power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
+power_tech_xml = /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK
 
 [csv_tags]
 mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh
index eb0c33265..d60a1e177 100755
--- a/fpga_flow/tuto_fpga_flow.sh
+++ b/fpga_flow/tuto_fpga_flow.sh
@@ -27,8 +27,7 @@ perl rewrite_path_in_file.pl -i $config_file	# Replace OPENFPGAPATHKEYWORD in th
 perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated	# Replace OPENFPGAPATHKEYWORD in the architecture file
 perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path	# Set the ff path in the architecture file
 echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path"
-perl rewrite_path_in_file.pl -i $ff_template_path -o $ff_path -k $dir_keyword $verilog_path	# Set the define path in the ff.v file
-
+perl rewrite_path_in_file.pl -i ${ff_template_path} -o ${ff_path} -k $dir_keyword $verilog_path	# Set the define path in the ff.v file
 
 # SRAM FPGA
 # TT case