From 417d534121197ca93b05d21a421062bf88855aac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 23 Apr 2020 16:15:45 -0600 Subject: [PATCH 1/4] fine tune mcnc example script to run Modelsim simulations easily --- .../OpenFPGAShellScripts/mcnc_example_script.openfpga | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga index 66b4c12fa..9a4f577f8 100644 --- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -37,7 +37,11 @@ build_fabric_bitstream --verbose # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC \ + --explicit_port_mapping \ + --include_timing \ + --include_signal_init + #--support_icarus_simulator # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists From 90f608baeaac8420bc091aba9d1e763ea255e357 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 23 Apr 2020 18:58:39 -0600 Subject: [PATCH 2/4] changing task mcnc file for debugging (temporarily now) Will be corrected later --- .../mcnc_big20/config/task.conf | 48 +++++++++---------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf index f2a92e6b9..5028283fb 100644 --- a/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf @@ -21,30 +21,30 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif -# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file -bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif -# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file -bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif -bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif -bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif -# VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file -bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif -bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif -bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif -bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif -bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif -bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif -bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif -# Passed -#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif -bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif -bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif -bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif -bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif -bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif +#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif +#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif +#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif +## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file +#bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif +## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file +#bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif +#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif +#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif +## VPR remove buffers which are in act file and create a new net. Then VPR errors out by saying the new net does not exist in act file +#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif +#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif +#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif +#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif +#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif +#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif +#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif +## Passed +bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif +#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif +#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif +#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif +#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif [SYNTHESIS_PARAM] # Benchmark alu4 From 87b17fc25f2944012d85e1d0da18cfd54488e056 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 23 Apr 2020 18:59:09 -0600 Subject: [PATCH 3/4] add netlist manager data structure --- openfpga/src/base/netlist_manager.cpp | 201 ++++++++++++++++++++++++ openfpga/src/base/netlist_manager.h | 107 +++++++++++++ openfpga/src/base/netlist_manager_fwd.h | 25 +++ 3 files changed, 333 insertions(+) create mode 100644 openfpga/src/base/netlist_manager.cpp create mode 100644 openfpga/src/base/netlist_manager.h create mode 100644 openfpga/src/base/netlist_manager_fwd.h diff --git a/openfpga/src/base/netlist_manager.cpp b/openfpga/src/base/netlist_manager.cpp new file mode 100644 index 000000000..b7860d14f --- /dev/null +++ b/openfpga/src/base/netlist_manager.cpp @@ -0,0 +1,201 @@ +/****************************************************************************** + * This files includes memeber functions for data structure NetlistManager + ******************************************************************************/ +#include + +#include "vtr_assert.h" +#include "netlist_manager.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/****************************************************************************** + * Public aggregators + ******************************************************************************/ +/* Find all the netlists */ +NetlistManager::netlist_range NetlistManager::netlists() const { + return vtr::make_range(netlist_ids_.begin(), netlist_ids_.end()); +} + +/* Find all the modules that are included in a netlist */ +std::vector NetlistManager::netlist_modules(const NetlistId& netlist) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + return included_module_ids_[netlist]; +} + + +/****************************************************************************** + * Public accessors + ******************************************************************************/ +/* Find the name of a netlist */ +std::string NetlistManager::netlist_name(const NetlistId& netlist) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + return netlist_names_[netlist]; +} + +/* Find a netlist by its name */ +NetlistId NetlistManager::find_netlist(const std::string& netlist_name) const { + if (name_id_map_.find(netlist_name) != name_id_map_.end()) { + /* Found, return the id */ + return name_id_map_.at(netlist_name); + } + /* Not found, return an invalid id */ + return NetlistId::INVALID(); +} + +NetlistManager::e_netlist_type NetlistManager::netlist_type(const NetlistId& netlist) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + return netlist_types_[netlist]; +} + +/* Find if a module belongs to a netlist */ +bool NetlistManager::is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + for (const ModuleId& included_module : included_module_ids_[netlist]) { + /* Already in the netlist, return true */ + if (module == included_module) { + return true; + } + } + + /* Not in the netlist, return false */ + return false; +} + +/* Find the netlist that a module belongs to */ +NetlistId NetlistManager::find_module_netlist(const ModuleId& module) const { + /* Find if the module has been added to a netlist. If used, return false! */ + /* Not found, return an invalid value */ + if ( module_netlist_map_.end() + != module_netlist_map_.find(module)) { + return NetlistId::INVALID(); + } + return module_netlist_map_.at(module); +} + + +/* Find all the preprocessing flags that are included in a netlist */ +std::vector NetlistManager::netlist_preprocessing_flags(const NetlistId& netlist) const { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + std::vector flags; + + for (const PreprocessingFlagId& flag_id : included_preprocessing_flag_ids_[netlist]) { + VTR_ASSERT(true == valid_preprocessing_flag_id(flag_id)); + flags.push_back(preprocessing_flag_names_[flag_id]); + } + + return flags; +} + +/****************************************************************************** + * Public mutators + ******************************************************************************/ +/* Add a netlist to the library */ +NetlistId NetlistManager::add_netlist(const std::string& name) { + /* Find if the name has been used. If used, return an invalid Id! */ + std::map::iterator it = name_id_map_.find(name); + if (it != name_id_map_.end()) { + return NetlistId::INVALID(); + } + + /* Create a new id */ + NetlistId netlist = NetlistId(netlist_ids_.size()); + netlist_ids_.push_back(netlist); + + /* Allocate related attributes */ + netlist_names_.push_back(name); + netlist_types_.push_back(NUM_NETLIST_TYPES); + included_module_ids_.emplace_back(); + included_preprocessing_flag_ids_.emplace_back(); + + /* Register in the name-to-id map */ + name_id_map_[name] = netlist; + + return netlist; +} + +void NetlistManager::set_netlist_type(const NetlistId& netlist, + const e_netlist_type& type) { + VTR_ASSERT(true == valid_netlist_id(netlist)); + netlist_types_[netlist] = type; +} + +/* Add a module to a netlist in the library */ +bool NetlistManager::add_netlist_module(const NetlistId& netlist, const ModuleId& module) { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + /* Find if the module already in the netlist */ + std::vector::iterator module_it = std::find(included_module_ids_[netlist].begin(), included_module_ids_[netlist].end(), module); + if (module_it != included_module_ids_[netlist].end()) { + /* Already in the netlist, nothing to do */ + return true; + } + /* Try to register it in module-to-netlist map */ + /* Find if the module has been added to a netlist. If used, return false! */ + std::map::iterator map_it = module_netlist_map_.find(module); + if (map_it != module_netlist_map_.end()) { + return false; + } + + /* Does not exist! Should add it to the list */ + included_module_ids_[netlist].push_back(module); + /* Register it in module-to-netlist map */ + module_netlist_map_[module] = netlist; + return true; +} + +/* Add a pre-processing flag to a netlist */ +void NetlistManager::add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag) { + VTR_ASSERT(true == valid_netlist_id(netlist)); + + PreprocessingFlagId flag = PreprocessingFlagId(preprocessing_flag_ids_.size()); + + /* Find if the module already in the netlist */ + for (const PreprocessingFlagId& id : preprocessing_flag_ids_) { + if (0 != preprocessing_flag.compare(preprocessing_flag_names_[id])) { + continue; + } + /* Already in the list of pre-processing flags, push it ot the */ + flag = id; + break; + } + + /* Update the list if we need */ + if (flag == PreprocessingFlagId(preprocessing_flag_ids_.size())) { + preprocessing_flag_ids_.push_back(flag); + preprocessing_flag_names_.push_back(preprocessing_flag); + } + + /* Check if the flag is already in the netlist */ + std::vector::iterator it = std::find(included_preprocessing_flag_ids_[netlist].begin(), included_preprocessing_flag_ids_[netlist].end(), flag); + if (it == included_preprocessing_flag_ids_[netlist].end()) { + /* Not in the list, we add it */ + included_preprocessing_flag_ids_[netlist].push_back(flag); + } +} + +/****************************************************************************** + * Public validators/invalidators + ******************************************************************************/ +bool NetlistManager::valid_netlist_id(const NetlistId& netlist) const { + return (size_t(netlist) < netlist_ids_.size()) && (netlist == netlist_ids_[netlist]); +} + +/****************************************************************************** + * Private validators/invalidators + ******************************************************************************/ +bool NetlistManager::valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const { + return (size_t(flag) < preprocessing_flag_ids_.size()) && (flag == preprocessing_flag_ids_[flag]); +} + +void NetlistManager::invalidate_name2id_map() { + name_id_map_.clear(); +} + +void NetlistManager::invalidate_module2netlist_map() { + module_netlist_map_.clear(); +} + +} /* end namespace openfpga */ diff --git a/openfpga/src/base/netlist_manager.h b/openfpga/src/base/netlist_manager.h new file mode 100644 index 000000000..fad76d25a --- /dev/null +++ b/openfpga/src/base/netlist_manager.h @@ -0,0 +1,107 @@ +/****************************************************************************** + * This files includes data structures for netlist management. + * It keeps a list of netlists that have been created + * Each netlist includes a list of ids of modules that are stored in ModuleManager + * + * When we want to dump out a netlist in Verilog/SPICE format, + * the netlist manager can generate the dependency on other netlists + * This can help us tracking the dependency and generate `include` files easily + * + * Cross-reference: + * + * +---------+ +---------+ + * | | ModuleId | | + * | Netlist |-------------->| Module | + * | Manager | | Manager | + * | | | | + * +---------+ +---------+ + * + ******************************************************************************/ +#ifndef NETLIST_MANAGER_H +#define NETLIST_MANAGER_H + +#include +#include +#include +#include "vtr_vector.h" +#include "netlist_manager_fwd.h" +#include "module_manager.h" + +/* begin namespace openfpga */ +namespace openfpga { + +class NetlistManager { + public: /* Internal Types */ + /* Type of netlists */ + enum e_netlist_type { + SUBMODULE_NETLIST, + LOGIC_BLOCK_NETLIST, + ROUTING_MODULE_NETLIST, + TOP_MODULE_NETLIST, + TESTBENCH_NETLIST, + NUM_NETLIST_TYPES + }; + public: /* Types and ranges */ + typedef vtr::vector::const_iterator netlist_iterator; + typedef vtr::Range netlist_range; + + public: /* Public aggregators */ + /* Find all the netlists */ + netlist_range netlists() const; + /* Find all the modules that are included in a netlist */ + std::vector netlist_modules(const NetlistId& netlist) const; + /* Find all the preprocessing flags that are included in a netlist */ + std::vector netlist_preprocessing_flags(const NetlistId& netlist) const; + + public: /* Public accessors */ + /* Find the name of a netlist */ + std::string netlist_name(const NetlistId& netlist) const; + /* Find a netlist by its name */ + NetlistId find_netlist(const std::string& netlist_name) const; + /* Get the type of a netlist */ + e_netlist_type netlist_type(const NetlistId& netlist) const; + /* Find if a module belongs to a netlist */ + bool is_module_in_netlist(const NetlistId& netlist, const ModuleId& module) const; + /* Find the netlist that a module belongs to */ + NetlistId find_module_netlist(const ModuleId& module) const; + + public: /* Public mutators */ + /* Add a netlist to the library */ + NetlistId add_netlist(const std::string& name); + /* Set a netlist type */ + void set_netlist_type(const NetlistId& netlist, + const e_netlist_type& type); + /* Add a module to a netlist in the library */ + bool add_netlist_module(const NetlistId& netlist, const ModuleId& module); + /* Add a pre-processing flag to a netlist */ + void add_netlist_preprocessing_flag(const NetlistId& netlist, const std::string& preprocessing_flag); + + public: /* Public validators/invalidators */ + bool valid_netlist_id(const NetlistId& netlist) const; + + private: /* Private validators/invalidators */ + bool valid_preprocessing_flag_id(const PreprocessingFlagId& flag) const; + void invalidate_name2id_map(); + void invalidate_module2netlist_map(); + + private: /* Internal data */ + vtr::vector netlist_ids_; + vtr::vector netlist_names_; + vtr::vector netlist_types_; + + vtr::vector> included_module_ids_; + vtr::vector> included_preprocessing_flag_ids_; + + vtr::vector preprocessing_flag_ids_; + vtr::vector preprocessing_flag_names_; + + /* fast look-up for netlist */ + std::map name_id_map_; + /* fast look-up for modules in netlists */ + std::map module_netlist_map_; +}; + +} /* end namespace openfpga */ + +#endif + diff --git a/openfpga/src/base/netlist_manager_fwd.h b/openfpga/src/base/netlist_manager_fwd.h new file mode 100644 index 000000000..186e1792c --- /dev/null +++ b/openfpga/src/base/netlist_manager_fwd.h @@ -0,0 +1,25 @@ +/************************************************** + * This file includes only declarations for + * the data structures for netlist managers + * Please refer to netlist_manager.h for more details + *************************************************/ +#ifndef NETLIST_MANAGER_FWD_H +#define NETLIST_MANAGER_FWD_H + +#include "vtr_strong_id.h" + +/* begin namespace openfpga */ +namespace openfpga { + +/* Strong Ids for ModuleManager */ +struct netlist_id_tag; +struct preprocessing_flag_id_tag; + +typedef vtr::StrongId NetlistId; +typedef vtr::StrongId PreprocessingFlagId; + +class NetlistManager; + +} /* end namespace openfpga */ + +#endif From e811f8bb211c9d7c7420b411df1120942738a6db Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 23 Apr 2020 20:42:11 -0600 Subject: [PATCH 4/4] plug in netlist manager and now the include_netlist appears in one unique file --- openfpga/src/base/netlist_manager.cpp | 11 +++++ openfpga/src/base/netlist_manager.h | 2 + openfpga/src/base/openfpga_context.h | 8 +++ openfpga/src/base/openfpga_verilog.cpp | 4 +- openfpga/src/fpga_verilog/verilog_api.cpp | 22 ++++++--- openfpga/src/fpga_verilog/verilog_api.h | 5 +- .../verilog_auxiliary_netlists.cpp | 24 +++++++-- .../fpga_verilog/verilog_auxiliary_netlists.h | 4 +- .../src/fpga_verilog/verilog_decoders.cpp | 6 ++- openfpga/src/fpga_verilog/verilog_decoders.h | 3 +- .../fpga_verilog/verilog_essential_gates.cpp | 6 ++- .../fpga_verilog/verilog_essential_gates.h | 4 +- openfpga/src/fpga_verilog/verilog_grid.cpp | 30 ++++++++---- openfpga/src/fpga_verilog/verilog_grid.h | 4 +- openfpga/src/fpga_verilog/verilog_lut.cpp | 6 ++- openfpga/src/fpga_verilog/verilog_lut.h | 3 +- openfpga/src/fpga_verilog/verilog_memory.cpp | 6 ++- openfpga/src/fpga_verilog/verilog_memory.h | 3 +- openfpga/src/fpga_verilog/verilog_mux.cpp | 6 ++- openfpga/src/fpga_verilog/verilog_mux.h | 3 +- openfpga/src/fpga_verilog/verilog_routing.cpp | 49 ++++++++++++------- openfpga/src/fpga_verilog/verilog_routing.h | 7 ++- .../src/fpga_verilog/verilog_submodule.cpp | 21 ++++---- openfpga/src/fpga_verilog/verilog_submodule.h | 2 + .../src/fpga_verilog/verilog_top_module.cpp | 8 ++- .../src/fpga_verilog/verilog_top_module.h | 4 +- openfpga/src/fpga_verilog/verilog_wire.cpp | 6 ++- openfpga/src/fpga_verilog/verilog_wire.h | 3 +- 28 files changed, 184 insertions(+), 76 deletions(-) diff --git a/openfpga/src/base/netlist_manager.cpp b/openfpga/src/base/netlist_manager.cpp index b7860d14f..0b2e6ec45 100644 --- a/openfpga/src/base/netlist_manager.cpp +++ b/openfpga/src/base/netlist_manager.cpp @@ -74,6 +74,17 @@ NetlistId NetlistManager::find_module_netlist(const ModuleId& module) const { return module_netlist_map_.at(module); } +std::vector NetlistManager::netlists_by_type(const NetlistManager::e_netlist_type& netlist_type) const { + std::vector nlists; + + for (const NetlistId& nlist_id : netlist_ids_) { + if (netlist_type == netlist_types_[nlist_id]) { + nlists.push_back(nlist_id); + } + } + + return nlists; +} /* Find all the preprocessing flags that are included in a netlist */ std::vector NetlistManager::netlist_preprocessing_flags(const NetlistId& netlist) const { diff --git a/openfpga/src/base/netlist_manager.h b/openfpga/src/base/netlist_manager.h index fad76d25a..df2283e77 100644 --- a/openfpga/src/base/netlist_manager.h +++ b/openfpga/src/base/netlist_manager.h @@ -58,6 +58,8 @@ class NetlistManager { std::string netlist_name(const NetlistId& netlist) const; /* Find a netlist by its name */ NetlistId find_netlist(const std::string& netlist_name) const; + /* Find all the netlist in a given type */ + std::vector netlists_by_type(const e_netlist_type& netlist_type) const; /* Get the type of a netlist */ e_netlist_type netlist_type(const NetlistId& netlist) const; /* Find if a module belongs to a netlist */ diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h index d4320915f..2ea114410 100644 --- a/openfpga/src/base/openfpga_context.h +++ b/openfpga/src/base/openfpga_context.h @@ -12,6 +12,7 @@ #include "mux_library.h" #include "tile_direct.h" #include "module_manager.h" +#include "netlist_manager.h" #include "openfpga_flow_manager.h" #include "bitstream_manager.h" #include "device_rr_gsb.h" @@ -61,6 +62,7 @@ class OpenfpgaContext : public Context { const std::vector& fabric_bitstream() const { return fabric_bitstream_; } const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; } const std::unordered_map& net_activity() const { return net_activity_; } + const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; } public: /* Public mutators */ openfpga::Arch& mutable_arch() { return arch_; } openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; } @@ -77,6 +79,7 @@ class OpenfpgaContext : public Context { std::vector& mutable_fabric_bitstream() { return fabric_bitstream_; } openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; } std::unordered_map& mutable_net_activity() { return net_activity_; } + openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; } private: /* Internal data */ /* Data structure to store information from read_openfpga_arch library */ openfpga::Arch arch_; @@ -113,6 +116,11 @@ class OpenfpgaContext : public Context { openfpga::BitstreamManager bitstream_manager_; std::vector fabric_bitstream_; + /* Netlist database + * TODO: Each format should have an independent entry + */ + openfpga::NetlistManager verilog_netlists_; + /* Net activities of users' implementation */ std::unordered_map net_activity_; diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index c79b68fc2..9a877c9f2 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -45,6 +45,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx, options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); fpga_fabric_verilog(openfpga_ctx.mutable_module_graph(), + openfpga_ctx.mutable_verilog_netlists(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), g_vpr_ctx.device(), @@ -82,7 +83,8 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); - fpga_verilog_testbench(openfpga_ctx.module_graph(), + fpga_verilog_testbench(openfpga_ctx.verilog_netlists(), + openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(), openfpga_ctx.fabric_bitstream(), g_vpr_ctx.atom(), diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index c37b68888..d2823df48 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -51,6 +51,7 @@ namespace openfpga { * We should think clearly about how to handle them for both Verilog and SPICE generators! ********************************************************************/ void fpga_fabric_verilog(ModuleManager& module_manager, + NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const DeviceContext& device_ctx, @@ -88,33 +89,38 @@ void fpga_fabric_verilog(ModuleManager& module_manager, * the module manager. * Without the modules in the module manager, core logic generation is not possible!!! */ - print_verilog_submodule(module_manager, mux_lib, circuit_lib, + print_verilog_submodule(module_manager, netlist_manager, + mux_lib, circuit_lib, src_dir_path, submodule_dir_path, options); /* Generate routing blocks */ if (true == options.compress_routing()) { - print_verilog_unique_routing_modules(const_cast(module_manager), + print_verilog_unique_routing_modules(netlist_manager, + const_cast(module_manager), device_rr_gsb, src_dir_path, rr_dir_path, options.explicit_port_mapping()); } else { VTR_ASSERT(false == options.compress_routing()); - print_verilog_flatten_routing_modules(const_cast(module_manager), + print_verilog_flatten_routing_modules(netlist_manager, + const_cast(module_manager), device_rr_gsb, src_dir_path, rr_dir_path, options.explicit_port_mapping()); } /* Generate grids */ - print_verilog_grids(const_cast(module_manager), + print_verilog_grids(netlist_manager, + const_cast(module_manager), device_ctx, device_annotation, src_dir_path, lb_dir_path, options.explicit_port_mapping(), options.verbose_output()); /* Generate FPGA fabric */ - print_verilog_top_module(const_cast(module_manager), + print_verilog_top_module(netlist_manager, + const_cast(module_manager), src_dir_path, options.explicit_port_mapping()); @@ -134,7 +140,8 @@ void fpga_fabric_verilog(ModuleManager& module_manager, * This testbench is created for quick verification and formal verification purpose. * - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated ********************************************************************/ -void fpga_verilog_testbench(const ModuleManager& module_manager, +void fpga_verilog_testbench(const NetlistManager& netlist_manager, + const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const std::vector& fabric_bitstream, const AtomContext& atom_ctx, @@ -219,7 +226,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager, } /* Generate a Verilog file including all the netlists that have been generated */ - print_include_netlists(src_dir_path, + print_include_netlists(netlist_manager, + src_dir_path, netlist_name, options.reference_benchmark_file_path(), circuit_lib); diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index 66eb069ba..c9d194dff 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -12,6 +12,7 @@ #include "vpr_context.h" #include "vpr_device_annotation.h" #include "device_rr_gsb.h" +#include "netlist_manager.h" #include "module_manager.h" #include "bitstream_manager.h" #include "simulation_setting.h" @@ -28,6 +29,7 @@ namespace openfpga { void fpga_fabric_verilog(ModuleManager& module_manager, + NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const DeviceContext& device_ctx, @@ -35,7 +37,8 @@ void fpga_fabric_verilog(ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const FabricVerilogOption& options); -void fpga_verilog_testbench(const ModuleManager& module_manager, +void fpga_verilog_testbench(const NetlistManager& netlist_manager, + const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const std::vector& fabric_bitstream, const AtomContext& atom_ctx, diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp index fd01a462f..ba2483ca7 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp @@ -29,7 +29,8 @@ namespace openfpga { * and user-defined. * Some netlists are open to compile under specific preprocessing flags *******************************************************************/ -void print_include_netlists(const std::string& src_dir, +void print_include_netlists(const NetlistManager& netlist_manager, + const std::string& src_dir, const std::string& circuit_name, const std::string& reference_benchmark_file, const CircuitLibrary& circuit_lib) { @@ -55,24 +56,37 @@ void print_include_netlists(const std::string& src_dir, fp << std::endl; /* Include all the user-defined netlists */ + print_verilog_comment(fp, std::string("------ Include user-defined netlists -----")); for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) { print_verilog_include_netlist(fp, user_defined_netlist); } /* Include all the primitive modules */ - print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_SUBMODULE_DIR_NAME) + std::string(SUBMODULE_VERILOG_FILE_NAME)); + print_verilog_comment(fp, std::string("------ Include primitive module netlists -----")); + for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) { + print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id)); + } fp << std::endl; /* Include all the CLB, heterogeneous block modules */ - print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_LB_DIR_NAME) + std::string(LOGIC_BLOCK_VERILOG_FILE_NAME)); + print_verilog_comment(fp, std::string("------ Include logic block netlists -----")); + for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) { + print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id)); + } fp << std::endl; /* Include all the routing architecture modules */ - print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_RR_DIR_NAME) + std::string(ROUTING_VERILOG_FILE_NAME)); + print_verilog_comment(fp, std::string("------ Include routing module netlists -----")); + for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) { + print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id)); + } fp << std::endl; /* Include FPGA top module */ - print_verilog_include_netlist(fp, src_dir + generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX))); + print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----")); + for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) { + print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id)); + } fp << std::endl; /* Include reference benchmark netlist only when auto-check flag is enabled */ diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h index 291ca8915..ed1317862 100644 --- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h +++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h @@ -7,6 +7,7 @@ #include #include "circuit_library.h" #include "fabric_verilog_options.h" +#include "netlist_manager.h" #include "verilog_testbench_options.h" /******************************************************************** @@ -16,7 +17,8 @@ /* begin namespace openfpga */ namespace openfpga { -void print_include_netlists(const std::string& src_dir, +void print_include_netlists(const NetlistManager& netlist_manager, + const std::string& src_dir, const std::string& circuit_name, const std::string& reference_benchmark_file, const CircuitLibrary& circuit_lib); diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp index e9b9f6d02..0e993a3d3 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.cpp +++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp @@ -162,7 +162,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp, * See more details in the function print_verilog_mux_local_decoder() for more details ***************************************************************************************/ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, @@ -223,7 +223,9 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h index 271e7aa5c..f8d559f4d 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.h +++ b/openfpga/src/fpga_verilog/verilog_decoders.h @@ -12,6 +12,7 @@ #include "mux_graph.h" #include "mux_library.h" #include "module_manager.h" +#include "netlist_manager.h" /******************************************************************** * Function declaration @@ -21,7 +22,7 @@ namespace openfpga { void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index a84d02bdf..20be3e7e4 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -526,7 +526,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager * etc. ***********************************************/ void print_verilog_submodule_essentials(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { @@ -577,7 +577,9 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager, fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h index b7f9b519a..b267d0e6e 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.h +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h @@ -6,6 +6,8 @@ *******************************************************************/ #include #include "circuit_library.h" +#include "module_manager.h" +#include "netlist_manager.h" /******************************************************************** * Function declaration @@ -15,7 +17,7 @@ namespace openfpga { void print_verilog_submodule_essentials(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib); diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 20cdd02f4..0cf509bde 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -194,8 +194,8 @@ void rec_print_verilog_logical_tile(std::fstream& fp, * for the logical tile (pb_graph/pb_type) *****************************************************************************/ static -void print_verilog_logical_tile_netlist(const ModuleManager& module_manager, - std::vector& netlist_names, +void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const VprDeviceAnnotation& device_annotation, const std::string& verilog_dir, const std::string& subckt_dir, @@ -243,7 +243,9 @@ void print_verilog_logical_tile_netlist(const ModuleManager& module_manager, fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST); VTR_LOG("Done\n"); VTR_LOG("\n"); @@ -258,8 +260,8 @@ void print_verilog_logical_tile_netlist(const ModuleManager& module_manager, * the I/O block locates at. *****************************************************************************/ static -void print_verilog_physical_tile_netlist(const ModuleManager& module_manager, - std::vector& netlist_names, +void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const std::string& verilog_dir, const std::string& subckt_dir, t_physical_tile_type_ptr phy_block_type, @@ -319,7 +321,9 @@ void print_verilog_physical_tile_netlist(const ModuleManager& module_manager, fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST); VTR_LOG("Done\n"); } @@ -330,7 +334,8 @@ void print_verilog_physical_tile_netlist(const ModuleManager& module_manager, * 2. Only one module for each CLB (FILL_TYPE) * 3. Only one module for each heterogeneous block ****************************************************************************/ -void print_verilog_grids(const ModuleManager& module_manager, +void print_verilog_grids(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation, const std::string& verilog_dir, @@ -354,7 +359,8 @@ void print_verilog_grids(const ModuleManager& module_manager, if (nullptr == logical_tile.pb_graph_head) { continue; } - print_verilog_logical_tile_netlist(module_manager, netlist_names, + print_verilog_logical_tile_netlist(netlist_manager, + module_manager, device_annotation, verilog_dir, subckt_dir, logical_tile.pb_graph_head, @@ -387,7 +393,8 @@ void print_verilog_grids(const ModuleManager& module_manager, std::set io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile); for (const e_side& io_type_side : io_type_sides) { - print_verilog_physical_tile_netlist(module_manager, netlist_names, + print_verilog_physical_tile_netlist(netlist_manager, + module_manager, verilog_dir, subckt_dir, &physical_tile, io_type_side, @@ -396,7 +403,8 @@ void print_verilog_grids(const ModuleManager& module_manager, continue; } else { /* For CLB and heterogenenous blocks */ - print_verilog_physical_tile_netlist(module_manager, netlist_names, + print_verilog_physical_tile_netlist(netlist_manager, + module_manager, verilog_dir, subckt_dir, &physical_tile, NUM_SIDES, @@ -408,6 +416,7 @@ void print_verilog_grids(const ModuleManager& module_manager, VTR_LOG("\n"); /* Output a header file for all the logic blocks */ + /* std::string grid_verilog_fname(LOGIC_BLOCK_VERILOG_FILE_NAME); VTR_LOG("Writing header file for grid Verilog modules '%s' ...", grid_verilog_fname.c_str()); @@ -415,6 +424,7 @@ void print_verilog_grids(const ModuleManager& module_manager, subckt_dir.c_str(), grid_verilog_fname.c_str()); VTR_LOG("Done\n"); + */ } } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_grid.h b/openfpga/src/fpga_verilog/verilog_grid.h index da8ea09fa..6d2843628 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.h +++ b/openfpga/src/fpga_verilog/verilog_grid.h @@ -7,6 +7,7 @@ #include #include "vpr_context.h" #include "module_manager.h" +#include "netlist_manager.h" #include "vpr_device_annotation.h" /******************************************************************** @@ -16,7 +17,8 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_grids(const ModuleManager& module_manager, +void print_verilog_grids(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index a849c5827..fabe9340e 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -30,7 +30,7 @@ namespace openfpga { * in the circuit library ********************************************************************/ void print_verilog_submodule_luts(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir, @@ -70,7 +70,9 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h index 7c8b85b79..e9ba3465a 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.h +++ b/openfpga/src/fpga_verilog/verilog_lut.h @@ -9,6 +9,7 @@ #include "circuit_library.h" #include "module_manager.h" +#include "netlist_manager.h" /******************************************************************** * Function declaration @@ -18,7 +19,7 @@ namespace openfpga { void print_verilog_submodule_luts(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir, diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index de0418481..53420a794 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -97,7 +97,7 @@ void print_verilog_mux_memory_module(const ModuleManager& module_manager, * memory-bank organization for the memories. ********************************************************************/ void print_verilog_submodule_memories(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, @@ -187,7 +187,9 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager, fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h index 9d29eb15f..a331e5687 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.h +++ b/openfpga/src/fpga_verilog/verilog_memory.h @@ -10,6 +10,7 @@ #include "mux_graph.h" #include "mux_library.h" #include "module_manager.h" +#include "netlist_manager.h" /******************************************************************** * Function declaration @@ -19,7 +20,7 @@ namespace openfpga { void print_verilog_submodule_memories(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index 1e58e3fc8..c85978722 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -1224,7 +1224,7 @@ void generate_verilog_mux_module(ModuleManager& module_manager, * multiplexers in the FPGA device **********************************************/ void print_verilog_submodule_muxes(ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, @@ -1273,7 +1273,9 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_mux.h b/openfpga/src/fpga_verilog/verilog_mux.h index 16e6c2f2a..c98fa77d0 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.h +++ b/openfpga/src/fpga_verilog/verilog_mux.h @@ -11,6 +11,7 @@ #include "mux_graph.h" #include "mux_library.h" #include "module_manager.h" +#include "netlist_manager.h" /******************************************************************** * Function declaration @@ -20,7 +21,7 @@ namespace openfpga { void print_verilog_submodule_muxes(ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index a3361fd06..8f74c0074 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -75,8 +75,8 @@ namespace openfpga { * ********************************************************************/ static -void print_verilog_routing_connection_box_unique_module(const ModuleManager& module_manager, - std::vector& netlist_names, +void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, @@ -111,7 +111,9 @@ void print_verilog_routing_connection_box_unique_module(const ModuleManager& mod fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST); } /********************************************************************* @@ -178,8 +180,8 @@ void print_verilog_routing_connection_box_unique_module(const ModuleManager& mod * ********************************************************************/ static -void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_manager, - std::vector& netlist_names, +void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, @@ -210,7 +212,9 @@ void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_ fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST); } /******************************************************************** @@ -218,8 +222,8 @@ void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_ * and build a module for each of them *******************************************************************/ static -void print_verilog_flatten_connection_block_modules(const ModuleManager& module_manager, - std::vector& netlist_names, +void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const std::string& verilog_dir, const std::string& subckt_dir, @@ -238,7 +242,8 @@ void print_verilog_flatten_connection_block_modules(const ModuleManager& module_ if (true != rr_gsb.is_cb_exist(cb_type)) { continue; } - print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, + print_verilog_routing_connection_box_unique_module(netlist_manager, + module_manager, verilog_dir, subckt_dir, rr_gsb, cb_type, @@ -256,7 +261,8 @@ void print_verilog_flatten_connection_block_modules(const ModuleManager& module_ * 1. Connection blocks * 2. Switch blocks *******************************************************************/ -void print_verilog_flatten_routing_modules(const ModuleManager& module_manager, +void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const std::string& verilog_dir, const std::string& subckt_dir, @@ -273,7 +279,8 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager, if (true != rr_gsb.is_sb_exist()) { continue; } - print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, + print_verilog_routing_switch_box_unique_module(netlist_manager, + module_manager, verilog_dir, subckt_dir, rr_gsb, @@ -281,10 +288,11 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager, } } - print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); - print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); + /* VTR_LOG("Writing header file for routing submodules '%s'...", ROUTING_VERILOG_FILE_NAME); print_verilog_netlist_include_header_file(netlist_names, @@ -292,6 +300,7 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager, ROUTING_VERILOG_FILE_NAME); VTR_LOG("Done\n"); VTR_LOG("\n"); + */ } @@ -305,7 +314,8 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager, * Note: this function SHOULD be called only when * the option compact_routing_hierarchy is turned on!!! *******************************************************************/ -void print_verilog_unique_routing_modules(const ModuleManager& module_manager, +void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const std::string& verilog_dir, const std::string& subckt_dir, @@ -316,7 +326,8 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager, /* Build unique switch block modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); - print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, + print_verilog_routing_switch_box_unique_module(netlist_manager, + module_manager, verilog_dir, subckt_dir, unique_mirror, @@ -327,7 +338,8 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager, for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); - print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, + print_verilog_routing_connection_box_unique_module(netlist_manager, + module_manager, verilog_dir, subckt_dir, unique_mirror, CHANX, @@ -338,19 +350,22 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager, for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); - print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, + print_verilog_routing_connection_box_unique_module(netlist_manager, + module_manager, verilog_dir, subckt_dir, unique_mirror, CHANY, use_explicit_port_map); } + /* VTR_LOG("Writing header file for routing submodules '%s'...", ROUTING_VERILOG_FILE_NAME); print_verilog_netlist_include_header_file(netlist_names, subckt_dir.c_str(), ROUTING_VERILOG_FILE_NAME); VTR_LOG("Done\n"); + */ VTR_LOG("\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_routing.h b/openfpga/src/fpga_verilog/verilog_routing.h index 2a1a58a66..a9f8fd6a1 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.h +++ b/openfpga/src/fpga_verilog/verilog_routing.h @@ -7,6 +7,7 @@ #include "mux_library.h" #include "module_manager.h" +#include "netlist_manager.h" #include "device_rr_gsb.h" /******************************************************************** @@ -16,13 +17,15 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_flatten_routing_modules(const ModuleManager& module_manager, +void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map); -void print_verilog_unique_routing_modules(const ModuleManager& module_manager, +void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, const std::string& verilog_dir, const std::string& subckt_dir, diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp index 099118e5f..b38750ab9 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp @@ -32,6 +32,7 @@ namespace openfpga { * 6. Verilog template ********************************************************************/ void print_verilog_submodule(ModuleManager& module_manager, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, @@ -44,12 +45,8 @@ void print_verilog_submodule(ModuleManager& module_manager, */ //add_user_defined_verilog_modules(module_manager, circuit_lib); - /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ - std::vector netlist_names; - - print_verilog_submodule_essentials(const_cast(module_manager), - netlist_names, + netlist_manager, verilog_dir, submodule_dir, circuit_lib); @@ -59,28 +56,28 @@ void print_verilog_submodule(ModuleManager& module_manager, * because local decoders modules will be instanciated in the MUX modules */ print_verilog_submodule_mux_local_decoders(const_cast(module_manager), - netlist_names, + netlist_manager, mux_lib, circuit_lib, verilog_dir, submodule_dir); - print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, circuit_lib, + print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib, verilog_dir, submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* LUTes */ print_verilog_submodule_luts(const_cast(module_manager), - netlist_names, circuit_lib, + netlist_manager, circuit_lib, verilog_dir, submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* Hard wires */ print_verilog_submodule_wires(const_cast(module_manager), - netlist_names, circuit_lib, + netlist_manager, circuit_lib, verilog_dir, submodule_dir); /* 4. Memories */ print_verilog_submodule_memories(const_cast(module_manager), - netlist_names, + netlist_manager, mux_lib, circuit_lib, verilog_dir, submodule_dir, fpga_verilog_opts.explicit_port_mapping()); @@ -93,9 +90,11 @@ void print_verilog_submodule(ModuleManager& module_manager, } /* Create a header file to include all the subckts */ - print_verilog_netlist_include_header_file(netlist_names, + /* + print_verilog_netlist_include_header_file(netlist_manager, submodule_dir.c_str(), SUBMODULE_VERILOG_FILE_NAME); + */ } } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h index 88e1ce965..d3de8b9d7 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.h +++ b/openfpga/src/fpga_verilog/verilog_submodule.h @@ -5,6 +5,7 @@ * Include header files that are required by function declaration *******************************************************************/ #include "module_manager.h" +#include "netlist_manager.h" #include "mux_library.h" #include "fabric_verilog_options.h" @@ -16,6 +17,7 @@ namespace openfpga { void print_verilog_submodule(ModuleManager& module_manager, + NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index 9bcfadc68..9596f20a3 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -34,7 +34,8 @@ namespace openfpga { * 4. Add module nets to connect datapath ports * 5. Add module nets/submodules to connect configuration ports *******************************************************************/ -void print_verilog_top_module(const ModuleManager& module_manager, +void print_verilog_top_module(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const std::string& verilog_dir, const bool& use_explicit_mapping) { /* Create a module as the top-level fabric, and add it to the module manager */ @@ -69,6 +70,11 @@ void print_verilog_top_module(const ModuleManager& module_manager, /* Close file handler */ fp.close(); + /* Add fname to the netlist name list */ + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::TOP_MODULE_NETLIST); + VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_top_module.h b/openfpga/src/fpga_verilog/verilog_top_module.h index 2fb451e16..95f73e815 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.h +++ b/openfpga/src/fpga_verilog/verilog_top_module.h @@ -6,6 +6,7 @@ *******************************************************************/ #include #include "module_manager.h" +#include "netlist_manager.h" /******************************************************************** * Function declaration @@ -14,7 +15,8 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_top_module(const ModuleManager& module_manager, +void print_verilog_top_module(NetlistManager& netlist_manager, + const ModuleManager& module_manager, const std::string& verilog_dir, const bool& use_explicit_mapping); diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp index 4f084fad9..d28b26f81 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.cpp +++ b/openfpga/src/fpga_verilog/verilog_wire.cpp @@ -93,7 +93,7 @@ void print_verilog_wire_module(const ModuleManager& module_manager, * Top-level function to print wire modules *******************************************************************/ void print_verilog_submodule_wires(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir) { @@ -128,7 +128,9 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager, fp.close(); /* Add fname to the netlist name list */ - netlist_names.push_back(verilog_fname); + NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname); + VTR_ASSERT(NetlistId::INVALID() != nlist_id); + netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST); VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h index 55c39fb30..62331d8b9 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.h +++ b/openfpga/src/fpga_verilog/verilog_wire.h @@ -9,6 +9,7 @@ #include "circuit_library.h" #include "module_manager.h" +#include "netlist_manager.h" /******************************************************************** * Function declaration @@ -18,7 +19,7 @@ namespace openfpga { void print_verilog_submodule_wires(const ModuleManager& module_manager, - std::vector& netlist_names, + NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir);