From 77304164f42ea464576278a1a985657914d80f44 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2024 10:13:41 -0700 Subject: [PATCH] [test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W --- .../homo_1clock_1reset_2layer/config/task.conf | 2 +- .../config/task.conf | 2 +- .../config/task.conf | 14 ++++---------- .../config/task.conf | 2 +- .../config/task.conf | 2 +- .../vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml | 4 ++-- 6 files changed, 10 insertions(+), 16 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf index 706b9b771..554a53d64 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf index ba2b9b5e5..622f0328e 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options=--disable_unused_spines diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf index 05ed91de3..038156d09 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= @@ -30,8 +30,7 @@ openfpga_route_clock_options= arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v [SYNTHESIS_PARAM] # Yosys script parameters @@ -41,13 +40,8 @@ bench_read_verilog_options_common = -nolatches bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys -bench0_top = counter -bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml -bench0_openfpga_verilog_testbench_port_mapping= - -bench1_top = counter -bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml -bench1_openfpga_verilog_testbench_port_mapping= +bench0_top = clk_gate +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_gate.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf index d01dfd35a..a3d9b1a48 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf index 706b9b771..554a53d64 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml openfpga_vpr_device_layout=2x2 -openfpga_vpr_route_chan_width=60 +openfpga_vpr_route_chan_width=32 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml openfpga_verilog_testbench_port_mapping=--explicit_port_mapping openfpga_route_clock_options= diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index b87a12a76..b105149b1 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -110,9 +110,9 @@ - + clb.reset clb.clk clb.O[0:3] clb.I[0:5] - clb.O[4:7] clb.I[6:11] + clb.O[4:7] clb.I[6:11]