From 76f446caece8f43071c7b2ca36b84b5802d830d6 Mon Sep 17 00:00:00 2001 From: tangxifan <tangxifan@gmail.com> Date: Mon, 25 Sep 2023 21:13:11 -0700 Subject: [PATCH] [core] fixed a bug --- libs/libarchopenfpga/src/tile_annotation.cpp | 2 +- .../build_grid_module_duplicated_pins.cpp | 18 +++++++++++------- .../src/fabric/build_grid_module_utils.cpp | 9 ++++++--- openfpga/src/fabric/build_grid_modules.cpp | 17 ++++++++++------- .../build_top_module_child_tile_instance.cpp | 13 ++++++++----- .../src/fabric/build_top_module_connection.cpp | 14 +++++++++----- 6 files changed, 45 insertions(+), 28 deletions(-) diff --git a/libs/libarchopenfpga/src/tile_annotation.cpp b/libs/libarchopenfpga/src/tile_annotation.cpp index fd5bd25d4..2ffacd1d0 100644 --- a/libs/libarchopenfpga/src/tile_annotation.cpp +++ b/libs/libarchopenfpga/src/tile_annotation.cpp @@ -108,7 +108,7 @@ bool TileAnnotation::is_tile_port_to_merge(const std::string& tile_name, if (result == tile_ports_to_merge_.end()) { return false; } - return result->second.end() == + return result->second.end() != std::find(result->second.begin(), result->second.end(), port_name); } diff --git a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp index 5a633eb0f..a8b2b8fd4 100644 --- a/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp +++ b/openfpga/src/fabric/build_grid_module_duplicated_pins.cpp @@ -99,13 +99,6 @@ void add_grid_module_duplicated_pb_type_ports( grid_type_descriptor, ipin); VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); - /* If the port is required to be merged, we deposit zero as subtile - * index */ - if (tile_annotation.is_tile_port_to_merge( - std::string(grid_type_descriptor->name), pin_info.get_name()) && - subtile_index != 0) { - continue; - } /* Generate the pin name * For each RECEIVER PIN or DRIVER PIN for direct connection, * we do not duplicate in these cases */ @@ -117,6 +110,17 @@ void add_grid_module_duplicated_pb_type_ports( (0. == find_physical_tile_pin_Fc(grid_type_descriptor, ipin)))) { std::string port_name = generate_grid_port_name( iwidth, iheight, subtile_index, side, pin_info); + /* If the port is required to be merged, we deposit zero as subtile + * index */ + if (tile_annotation.is_tile_port_to_merge( + std::string(grid_type_descriptor->name), pin_info.get_name())) { + if (subtile_index == 0) { + port_name = generate_grid_port_name( + 0, 0, 0, TOP, pin_info); + } else { + continue; + } + } BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_port, diff --git a/openfpga/src/fabric/build_grid_module_utils.cpp b/openfpga/src/fabric/build_grid_module_utils.cpp index 8c3dfe5ac..eacab5321 100644 --- a/openfpga/src/fabric/build_grid_module_utils.cpp +++ b/openfpga/src/fabric/build_grid_module_utils.cpp @@ -90,14 +90,17 @@ void add_grid_module_net_connect_pb_graph_pin( grid_type_descriptor, grid_pin_index); VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); + std::string grid_port_name = generate_grid_port_name( + pin_width, pin_height, subtile_index, side, pin_info); /* If the port is required to be merged, we only consider the source port to * be the subtile index of 0 */ if (tile_annotation.is_tile_port_to_merge( std::string(grid_type_descriptor->name), pin_info.get_name())) { - subtile_index = 0; + /* Exception: use top side for these merged ports */ + grid_port_name = generate_grid_port_name( + 0, 0, 0, TOP, pin_info); + VTR_LOG("Use source pin '%s'\n", grid_port_name.c_str()); } - std::string grid_port_name = generate_grid_port_name( - pin_width, pin_height, subtile_index, side, pin_info); ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id( diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 72f0df1a0..ad49cc63c 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -87,17 +87,20 @@ static void add_grid_module_pb_type_ports( int subtile_index = vpr_device_annotation.physical_tile_pin_subtile_index( grid_type_descriptor, ipin); - /* If the port is required to be merged, we deposit zero as subtile - * index */ - if (tile_annotation.is_tile_port_to_merge( - std::string(grid_type_descriptor->name), pin_info.get_name()) && - subtile_index != 0) { - continue; - } VTR_ASSERT(OPEN != subtile_index && subtile_index < grid_type_descriptor->capacity); std::string port_name = generate_grid_port_name( iwidth, iheight, subtile_index, side, pin_info); + /* If the port is required to be merged, we use a special index + * index */ + if (tile_annotation.is_tile_port_to_merge( + std::string(grid_type_descriptor->name), pin_info.get_name())) { + if (subtile_index == 0) { + port_name = generate_grid_port_name(0, 0, 0, TOP, pin_info); + } else { + continue; + } + } BasicPort grid_port(port_name, 0, 0); /* Add the port to the module */ module_manager.add_port(grid_module, grid_port, diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 8cf04a36d..9b59019cb 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1398,17 +1398,20 @@ static int build_top_module_global_net_for_given_tile_module( vpr_device_annotation.physical_tile_pin_port_info(physical_tile, grid_pin_index); VTR_ASSERT(true == grid_pin_info.is_valid()); - if (tile_annotation.is_tile_port_to_merge( - std::string(physical_tile->name), grid_pin_info.get_name()) && - subtile_index != 0) { - continue; - } /* Build nets */ for (const e_side& pin_side : pin_sides) { std::string grid_port_name = generate_grid_port_name(grid_pin_width, grid_pin_height, subtile_index, pin_side, grid_pin_info); + if (tile_annotation.is_tile_port_to_merge( + std::string(physical_tile->name), grid_pin_info.get_name())) { + if (subtile_index != 0) { + grid_port_name = generate_grid_port_name(0, 0, 0, TOP, grid_pin_info); + } else { + continue; + } + } std::string tile_grid_port_name = generate_tile_module_port_name(grid_instance_name, grid_port_name); ModulePortId tile_grid_port_id = diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index 48b5f1cd6..49eeee658 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -944,17 +944,21 @@ static int build_top_module_global_net_for_given_grid_module( vpr_device_annotation.physical_tile_pin_port_info(physical_tile, grid_pin_index); VTR_ASSERT(true == grid_pin_info.is_valid()); - if (tile_annotation.is_tile_port_to_merge( - std::string(physical_tile->name), grid_pin_info.get_name()) && - subtile_index != 0) { - continue; - } /* Build nets */ for (const e_side& pin_side : pin_sides) { std::string grid_port_name = generate_grid_port_name(grid_pin_width, grid_pin_height, subtile_index, pin_side, grid_pin_info); + if (tile_annotation.is_tile_port_to_merge( + std::string(physical_tile->name), grid_pin_info.get_name())) { + if (subtile_index != 0) { + grid_port_name = generate_grid_port_name(0, 0, 0, TOP, grid_pin_info); + } else { + continue; + } + } + ModulePortId grid_port_id = module_manager.find_module_port(grid_module, grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module,