diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt
new file mode 100644
index 000000000..00e6a7ce2
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt
@@ -0,0 +1,18 @@
+bram $__MY_DPRAM_1024x8
+  init 0
+  abits 10
+  dbits 8
+  groups 2
+  ports  1  1
+  wrmode 1  0
+  enable 1  1
+  transp 0  0
+  clocks 1  1
+  clkpol 1  1
+endbram
+
+match $__MY_DPRAM_1024x8
+  min efficiency 0
+  make_transp
+endmatch
+
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v
new file mode 100644
index 000000000..fdc8bef43
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v
@@ -0,0 +1,21 @@
+module $__MY_DPRAM_1024x8 (
+  output [7:0] B1DATA,
+  input CLK1,
+  input [9:0] B1ADDR,
+  input [9:0] A1ADDR,
+  input [7:0] A1DATA,
+  input A1EN,
+  input B1EN );
+
+  generate
+    dpram_1024x8 #() _TECHMAP_REPLACE_ (
+      .clk    (CLK1),
+      .wen    (A1EN),
+      .waddr    (A1ADDR),
+      .data_in    (A1DATA),
+      .ren    (B1EN),
+      .raddr    (B1ADDR),
+      .data_out    (B1DATA) );
+  endgenerate
+
+endmodule
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v
new file mode 100644
index 000000000..9d9c61636
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v
@@ -0,0 +1,59 @@
+//-----------------------------
+// Dual-port RAM 1024x8 bit (8Kbit)
+// Core logic
+//-----------------------------
+module dpram_1024x8_core (
+  input wclk,
+  input wen,
+  input [9:0] waddr,
+  input [7:0] data_in,
+  input rclk,
+  input ren,
+  input [9:0] raddr,
+  output [7:0] data_out );
+
+  reg [7:0] ram[1023:0];
+  reg [7:0] internal;
+
+  assign data_out = internal;
+
+  always @(posedge wclk) begin
+    if(wen) begin
+      ram[waddr] <= data_in;
+    end
+  end
+
+  always @(posedge rclk) begin
+    if(ren) begin
+      internal <= ram[raddr];
+    end
+  end
+
+endmodule
+
+//-----------------------------
+// Dual-port RAM 1024x8 bit (8Kbit) wrapper
+// where the read clock and write clock
+// are combined to a unified clock
+//-----------------------------
+module dpram_1024x8 (
+  input clk,
+  input wen,
+  input ren,
+  input [9:0] waddr,
+  input [9:0] raddr,
+  input [7:0] data_in,
+  output [7:0] data_out );
+
+    dpram_1024x8_core memory_0 (
+      .wclk    (clk),
+      .wen    (wen),
+      .waddr    (waddr),
+      .data_in  (data_in),
+      .rclk    (clk),
+      .ren    (ren),
+      .raddr    (raddr),
+      .data_out    (data_out) );
+
+endmodule
+
diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
index 5f8a12e5a..cd1f2e8f4 100644
--- a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
@@ -48,30 +48,4 @@ module dual_port_sram (
 
 endmodule
 
-//---------------------------------------
-// A single-port 32x8bit RAM 
-// This module is tuned for VTR's benchmarks
-//---------------------------------------
-module single_port_ram (
-	input clk,
-	input we,
-	input [4:0] addr,
-	input [7:0] data,
-	output [7:0] out );
 
-	reg [7:0] ram[31:0];
-	reg [7:0] internal;
-
-	assign out = internal;
-
-	always @(posedge clk) begin
-		if(wen) begin
-			ram[addr] <= data;
-		end
-
-		if(ren) begin
-			internal <= ram[addr];
-		end
-	end
-
-endmodule