Add verilog header sub_module.v file generation

vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_global.c

@@ -20,6 +20,7 @@ char* blif_testbench_verilog_file_postfix = "_blif_tb.v";
 char* logic_block_verilog_file_name = "logic_blocks.v";
 char* luts_verilog_file_name = "luts.v";
 char* routing_verilog_file_name = "routing.v";
+char* sub_module_verilog_file_name = "sub_module.v";
 char* muxes_verilog_file_name = "muxes.v";
 char* wires_verilog_file_name = "wires.v";
 char* essentials_verilog_file_name = "inv_buf_passgate.v";
@@ -50,5 +51,7 @@ t_llist* conf_bits_head = NULL;
 /* Linked-list that stores submodule Verilog file mames */
 t_llist* grid_verilog_subckt_file_path_head  = NULL;
 t_llist* routing_verilog_subckt_file_path_head = NULL;
+t_llist* submodule_verilog_subckt_file_path_head = NULL;
+
 
 int verilog_default_signal_init_value = 0;

vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_global.h

@@ -12,6 +12,8 @@ extern char* blif_testbench_verilog_file_postfix;
 extern char* logic_block_verilog_file_name;
 extern char* luts_verilog_file_name;
 extern char* routing_verilog_file_name;
+extern char* sub_module_verilog_file_name;
+extern char* muxes_verilog_file_name;
 extern char* muxes_verilog_file_name;
 extern char* wires_verilog_file_name;
 extern char* essentials_verilog_file_name;
@@ -42,6 +44,8 @@ extern t_llist* conf_bits_head;
 /* Linked-list that stores submodule Verilog file mames */
 extern t_llist* grid_verilog_subckt_file_path_head;
 extern t_llist* routing_verilog_subckt_file_path_head;
+extern t_llist* submodule_verilog_subckt_file_path_head;
+
 
 extern int verilog_default_signal_init_value;
 

vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.c

@@ -477,6 +477,9 @@ void dump_verilog_submodule_essentials(char* submodule_dir,
   /* Close file handler*/
   fclose(fp); 
 
+  /* Add fname to the linked list */
+  submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
+
   /* Free */
   
   return;
@@ -1999,6 +2002,9 @@ void dump_verilog_submodule_muxes(char* submodule_dir,
   vpr_printf(TIO_MESSAGE_INFO,"Min. MUX size = %d.\n",
              min_mux_size);
 
+  /* Add fname to the linked list */
+  submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
+
   /* remember to free the linked list*/
   free_muxes_llist(muxes_head);
   /* Free strings */
@@ -2205,6 +2211,9 @@ void dump_verilog_submodule_luts(char* submodule_dir,
   /* Close the file handler */
   fclose(fp);
 
+  /* Add fname to the linked list */
+  submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
+
   return;
 }
 
@@ -2337,6 +2346,9 @@ void dump_verilog_submodule_wires(char* subckt_dir,
   /* Close the file handler */
   fclose(fp);
 
+  /* Add fname to the linked list */
+  submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name);
+
   /*Free*/
   my_free(seg_index_str);
   my_free(seg_wire_subckt_name);
@@ -2378,6 +2390,14 @@ void dump_verilog_submodules(char* submodule_dir,
   dump_verilog_submodule_wires(submodule_dir, Arch.num_segments, Arch.Segments,
                                Arch.spice->num_spice_model, Arch.spice->spice_models);
 
+
+  /*Create a header file to include all the subckts */
+
+  vpr_printf(TIO_MESSAGE_INFO,"Generating header file for basic submodules...\n");
+  dump_verilog_subckt_header_file(submodule_verilog_subckt_file_path_head,
+                                  submodule_dir,
+                                  sub_module_verilog_file_name);
+
   return;
 }