diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 83d74d6ac..23abbc3ea 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -203,6 +203,7 @@ int fpga_verilog_testbench(const ModuleManager &module_manager,
                                        random_top_testbench_file_path,
                                        atom_ctx,
                                        netlist_annotation,
+                                       pin_constraints,
                                        simulation_setting,
                                        options.explicit_port_mapping());
   }
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
index eb20ccaec..9c4ad47e5 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
@@ -194,6 +194,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const AtomContext& atom_ctx,
                                         const VprNetlistAnnotation& netlist_annotation,
+                                        const PinConstraints& pin_constraints,
                                         const SimulationSetting& simulation_parameters,
                                         const bool& explicit_port_mapping) {
   std::string timer_message = std::string("Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by '") + circuit_name.c_str() + std::string("'");
@@ -232,7 +233,9 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
   std::vector<BasicPort> clock_ports = generate_verilog_testbench_clock_port(clock_port_names, std::string(DEFAULT_CLOCK_NAME));
 
   /* Add stimuli for reset, set, clock and iopad signals */
-  print_verilog_testbench_clock_stimuli(fp, simulation_parameters, 
+  print_verilog_testbench_clock_stimuli(fp,
+                                        pin_constraints, 
+                                        simulation_parameters, 
                                         clock_ports);
   print_verilog_testbench_random_stimuli(fp, atom_ctx,
                                          netlist_annotation, 
diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
index 775bc14d4..d89652df9 100644
--- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
+++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
@@ -6,6 +6,7 @@
  *******************************************************************/
 #include <string>
 #include "vpr_context.h"
+#include "pin_constraints.h"
 #include "simulation_setting.h"
 
 /********************************************************************
@@ -19,6 +20,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
                                         const std::string& verilog_fname,
                                         const AtomContext& atom_ctx,
                                         const VprNetlistAnnotation& netlist_annotation,
+                                        const PinConstraints& pin_constraints,
                                         const SimulationSetting& simulation_parameters,
                                         const bool& explicit_port_mapping);
 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
index 8f9e3df79..d46521ae7 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
@@ -476,6 +476,7 @@ void print_verilog_testbench_check(std::fstream& fp,
  * but be only used as a synchronizer in verification
  *******************************************************************/
 void print_verilog_testbench_clock_stimuli(std::fstream& fp,
+                                           const PinConstraints& pin_constraints,
                                            const SimulationSetting& simulation_parameters,
                                            const std::vector<BasicPort>& clock_ports) {
   /* Validate the file stream */
@@ -486,13 +487,23 @@ void print_verilog_testbench_clock_stimuli(std::fstream& fp,
 
     /* Find the corresponding clock frequency from the simulation parameters */
     float clk_freq_to_use = (0.5 / simulation_parameters.default_operating_clock_frequency()) / VERILOG_SIM_TIMESCALE;
-    /* FIXME: This could be buggy because the implementation clock names do NOT have to 
-     *        be the same as the clock definition in simulation settings!!!
+    /* Check pin constraints to see if this clock is constrained to a specific pin
+     * If constrained, 
+     * - connect this clock to default values if it is set to be OPEN
+     * - connect this clock to a specific clock source from simulation settings!!!
      */
-    for (const SimulationClockId& sim_clock_id : simulation_parameters.clocks()) {
-      /* If the clock name matches, we can use the clock frequency */
-      if (simulation_parameters.clock_port(sim_clock_id) == clock_port) {
-        clk_freq_to_use = (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / VERILOG_SIM_TIMESCALE;
+    VTR_ASSERT(1 == clock_port.get_width());
+    for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
+      if (clock_port.get_name() != pin_constraints.net(pin_constraint)) {
+        continue;
+      }
+      /* Skip all the unrelated pin constraints */
+      VTR_ASSERT(clock_port.get_name() == pin_constraints.net(pin_constraint));
+      /* Try to find which clock source is considered in simulation settings for this pin */
+      for (const SimulationClockId& sim_clock_id : simulation_parameters.clocks()) {
+        if (pin_constraints.pin(pin_constraint) == simulation_parameters.clock_port(sim_clock_id)) {
+          clk_freq_to_use = (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / VERILOG_SIM_TIMESCALE;
+        }
       }
     }
 
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
index 3683c473c..a2eca17cd 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h
@@ -12,6 +12,7 @@
 #include "vpr_context.h"
 #include "io_location_map.h"
 #include "vpr_netlist_annotation.h"
+#include "pin_constraints.h"
 #include "simulation_setting.h"
 
 /********************************************************************
@@ -76,6 +77,7 @@ void print_verilog_testbench_check(std::fstream& fp,
                                    const std::string& default_clock_name);
 
 void print_verilog_testbench_clock_stimuli(std::fstream& fp,
+                                           const PinConstraints& pin_constraints,
                                            const SimulationSetting& simulation_parameters,
                                            const std::vector<BasicPort>& clock_ports);