diff --git a/openfpga_flow/VerilogNetlists/config_latch_set.v b/openfpga_flow/VerilogNetlists/config_latch_set.v
new file mode 100644
index 000000000..945df2377
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/config_latch_set.v
@@ -0,0 +1,37 @@
+//-----------------------------------------------------
+// Design Name : config_latch
+// File Name : config_latch.v
+// Function : A Configurable Latch where data storage
+// can be updated when wl is enabled
+// Set is active high
+// Coder : Xifan TANG
+//-----------------------------------------------------
+module config_latch_set (
+ input set, // Reset input
+ input wl, // Data Enable
+ input bl, // Data Input
+ output Q, // Q output
+ output Qb // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (set or bl or wl) begin
+ if (set) begin
+ q_reg <= 1'b1;
+ end else if (1'b1 == wl) begin
+ q_reg <= bl;
+ end
+end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+// Wire q_reg to Q
+assign Q = q_reg;
+assign Qb = ~q_reg;
+`else
+assign Q = 1'bZ;
+assign Qb = !Q;
+`endif
+
+endmodule
diff --git a/openfpga_flow/VerilogNetlists/config_latch_set_reset.v b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v
new file mode 100644
index 000000000..ad9f75322
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/config_latch_set_reset.v
@@ -0,0 +1,41 @@
+//-----------------------------------------------------
+// Design Name : config_latch
+// File Name : config_latch.v
+// Function : A Configurable Latch where data storage
+// can be updated when wl is enabled
+// Reset is active high
+// Set is active high
+// Coder : Xifan TANG
+//-----------------------------------------------------
+module config_latch_set_reset (
+ input reset, // Reset input
+ input set, // Set input
+ input wl, // Data Enable
+ input bl, // Data Input
+ output Q, // Q output
+ output Qb // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (reset or set or bl or wl) begin
+ if (reset) begin
+ q_reg <= 1'b0;
+ end else if (set) begin
+ q_reg <= 1'b1;
+ end else if (1'b1 == wl) begin
+ q_reg <= bl;
+ end
+end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+// Wire q_reg to Q
+assign Q = q_reg;
+assign Qb = ~q_reg;
+`else
+assign Q = 1'bZ;
+assign Qb = !Q;
+`endif
+
+endmodule
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml
index a3ea99857..2785712a8 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml
@@ -146,7 +146,7 @@
-
+
@@ -161,13 +161,13 @@
-
+
-
+