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Updated format

This commit is contained in:
Ganesh Gore 2023-03-13 02:43:44 -06:00
parent 3bced9c055
commit 758222a193
1 changed files with 1 additions and 3 deletions
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4
openfpga_flow/scripts/run_fpga_task.py
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@ -360,21 +360,19 @@ def generate_each_task_actions(taskname):
for key, values in task_conf[eachset].items(): for key, values in task_conf[eachset].items():
command += ["--" + key, values] if values else ["--" + key] command += ["--" + key, values] if values else ["--" + key]
if "end_flow_with_test" in command: if "end_flow_with_test" in command:
# Verilog script is only required when end_flow_with_test defined # Verilog script is only required when end_flow_with_test defined
# Check if base verilog file exists # Check if base verilog file exists
if not SynthSection.get(bech_name + "_verilog"): if not SynthSection.get(bech_name + "_verilog"):
clean_up_and_exit( clean_up_and_exit(
"Missing argument %s for vpr_blif flow" % (bech_name + "_verilog") "Missing argument %s for vpr_blif flow" % (bech_name + "_verilog")
) )
# Set label for Sript Parameters # Set label for Sript Parameters
set_lbl = eachset.replace("SCRIPT_PARAM", "") set_lbl = eachset.replace("SCRIPT_PARAM", "")
set_lbl = set_lbl[1:] if set_lbl else "Common" set_lbl = set_lbl[1:] if set_lbl else "Common"
script_para_list[set_lbl] = command script_para_list[set_lbl] = command
CurrBenchPara["verilog_file"] = SynthSection.get(bech_name + "_verilog") CurrBenchPara["verilog_file"] = SynthSection.get(bech_name + "_verilog")
CurrBenchPara["script_params"] = script_para_list CurrBenchPara["script_params"] = script_para_list