riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Updated format

This commit is contained in:
Ganesh Gore 2023-03-13 02:43:44 -06:00
parent 3bced9c055
commit 758222a193
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/scripts/run_fpga_task.py
View File

@ -360,7 +360,6 @@ def generate_each_task_actions(taskname):
for key, values in task_conf[eachset].items(): for key, values in task_conf[eachset].items():
command += ["--" + key, values] if values else ["--" + key] command += ["--" + key, values] if values else ["--" + key]
if "end_flow_with_test" in command: if "end_flow_with_test" in command:
# Verilog script is only required when end_flow_with_test defined # Verilog script is only required when end_flow_with_test defined
# Check if base verilog file exists # Check if base verilog file exists
@ -374,7 +373,6 @@ def generate_each_task_actions(taskname):
set_lbl = set_lbl[1:] if set_lbl else "Common" set_lbl = set_lbl[1:] if set_lbl else "Common"
script_para_list[set_lbl] = command script_para_list[set_lbl] = command
CurrBenchPara["verilog_file"] = SynthSection.get(bech_name + "_verilog") CurrBenchPara["verilog_file"] = SynthSection.get(bech_name + "_verilog")
CurrBenchPara["script_params"] = script_para_list CurrBenchPara["script_params"] = script_para_list