[script] enable shared library for openfpga
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@ -149,6 +149,7 @@ jobs:
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build/vtr-verilog-to-routing/vpr/libvpr.a
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build/vtr-verilog-to-routing/vpr/vpr
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build/openfpga/libopenfpga.a
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build/openfpga/libopenfpga_shared.so
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build/openfpga/openfpga
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yosys/install/share
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yosys/install/bin
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@ -28,6 +28,7 @@ __pycache__/
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*.d
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*.o
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*.a
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*.so
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vpr7_x2p/vpr/vpr
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vpr7_x2p/printhandler/printhandlerdemo
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vpr7_x2p/libarchfpga/read_arch
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@ -11,6 +11,7 @@ files_to_dirs(LIB_HEADERS LIB_INCLUDE_DIRS)
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list(REMOVE_ITEM LIB_SOURCES ${EXEC_SOURCE})
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#Create the library
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#Static linked library for other C++ libraries
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add_library(libopenfpga STATIC
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${LIB_HEADERS}
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${LIB_SOURCES})
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@ -31,6 +32,28 @@ target_link_libraries(libopenfpga
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libpugixml
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libvpr)
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#Dynamic linked library for high-level interfaces, e.g., Tcl
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add_library(libopenfpga_shared SHARED
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${LIB_HEADERS}
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${LIB_SOURCES})
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target_include_directories(libopenfpga_shared PUBLIC ${LIB_INCLUDE_DIRS})
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set_target_properties(libopenfpga_shared PROPERTIES PREFIX "") #Avoid extra 'lib' prefix
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#Specify link-time dependancies
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target_link_libraries(libopenfpga_shared
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libarchopenfpga
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libopenfpgashell
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libopenfpgautil
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libfabrickey
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libfpgabitstream
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libini
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libpcf
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libvtrutil
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libbusgroup
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libpugixml
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libvpr)
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#Create the test executable
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add_executable(openfpga ${EXEC_SOURCE})
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target_link_libraries(openfpga libopenfpga)
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