diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v
index 3e767d8c4..6f62e627c 100644
--- a/openfpga_flow/VerilogNetlists/dff.v
+++ b/openfpga_flow/VerilogNetlists/dff.v
@@ -237,6 +237,49 @@ end
endmodule //End Of Module
+//-----------------------------------------------------
+// Function : D-type flip-flop with
+// - asynchronous active high reset
+// - asynchronous active high set
+// - scan-chain input
+// - a scan-chain enable
+//-----------------------------------------------------
+module SDFFSR (
+ input SET, // Set input
+ input RST, // Reset input
+ input CK, // Clock Input
+ input SE, // Scan-chain Enable
+ input D, // Data Input
+ input SI, // Scan-chain input
+ output Q, // Q output
+ output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+ q_reg <= 1'b0;
+end else if (SET) begin
+ q_reg <= 1'b1;
+end else if (SE) begin
+ q_reg <= SI;
+end else begin
+ q_reg <= D;
+end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+// Wire q_reg to Q
+ assign Q = q_reg;
+ assign QN = !Q;
+`else
+ assign Q = 1'bZ;
+ assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml
index ccaa8b66c..3ed8a652b 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml
@@ -146,17 +146,18 @@
-
+
-
+
-
+
+