From d6464fa7ccd2a1870a378ff2c24bc38a940ff58e Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Thu, 4 Mar 2021 03:16:21 -0800 Subject: [PATCH 1/6] update yosys submodule --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index 3a9968de9..e664dd4f3 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit 3a9968de914973f65928b724e889b134f8a4f2ae +Subproject commit e664dd4f34bfac7fca18939d9abf064f5790e0cf From c4b83aeaa9c7c87df0d1cb69f4e51e3bab7d2517 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Tue, 9 Mar 2021 00:46:40 -0800 Subject: [PATCH 2/6] bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type --- openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 824d92301..d58a27fbd 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_circuit_format=eblif -yosys_args = -no_adder -family qlf_k4n8 +yosys_args = -no_adder -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml From 7f4c20ff33a3b201b2d8386bf07e25981235381e Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Tue, 9 Mar 2021 10:37:06 -0800 Subject: [PATCH 3/6] comment out desings that utilize local async reset/preset --- .../tasks/quicklogic_tests/flow_test/config/task.conf | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index d58a27fbd..43e7649b8 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -33,7 +33,8 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/c bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v -bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v +#cavlc_top requires async reset/preset +#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v # counter120bitx5 requires 5 clocks #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v @@ -41,8 +42,10 @@ bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_ bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v -bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v -bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v +#i2c_master_top requires async reset/preset +#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v +#iir requires async reset/preset +#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v # sdc_controller requires 4 clocks From 608bd1f658cc6701e7e05bae9a49e611bdb77710 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Tue, 9 Mar 2021 19:24:01 -0800 Subject: [PATCH 4/6] comment out desings that utilize local async reset/preset --- .../tasks/quicklogic_tests/flow_test/config/task.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 43e7649b8..c21d40b7e 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -46,7 +46,8 @@ bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v #iir requires async reset/preset #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v -bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v +#jpeg_qnr requires async reset/preset +#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v # sdc_controller requires 4 clocks #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v From db8ea86b2f51f544eb0152da62260d35ab7f80ea Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Wed, 10 Mar 2021 10:04:45 -0800 Subject: [PATCH 5/6] update tests to use no_ff_map and remove tests that need async set/reset for now --- .../quicklogic_tests/counter_5clock_test/config/task.conf | 2 +- .../tasks/quicklogic_tests/flow_test/config/task.conf | 4 ++++ .../tasks/quicklogic_tests/lut_adder_test/config/task.conf | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf index 92c91491e..d36b504c5 100644 --- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml -yosys_args = -no_adder -family qlf_k4n8 +yosys_args = -no_adder -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index c21d40b7e..e3400e574 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -63,6 +63,7 @@ bench5_top = rs_decoder_top bench6_top = top_module bench7_top = sha256 bench8_top = cavlc_top +#bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench9_top = cf_fft_256_8 #bench10_top = counter120bitx5 #bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys @@ -71,8 +72,11 @@ bench12_top = dct_mac bench13_top = des_perf bench14_top = diffeq_f_systemC bench15_top = i2c_master_top +#bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench16_top = iir +#bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench17_top = jpeg_qnr +#bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench18_top = multi_enc_decx2x4 # sdc_controller requires 4 clocks #bench19_top = sdc_controller diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 6f711649b..c00c2caed 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml openfpga_vpr_circuit_format=eblif -yosys_args = -family qlf_k4n8 +yosys_args = -family qlf_k4n8 -no_ff_map [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml From b138d366251d40ef60c88ed8fb7fa539a15b0088 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Wed, 10 Mar 2021 10:14:42 -0800 Subject: [PATCH 6/6] update yosys module with async preset support --- yosys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/yosys b/yosys index e664dd4f3..f44a4f908 160000 --- a/yosys +++ b/yosys @@ -1 +1 @@ -Subproject commit e664dd4f34bfac7fca18939d9abf064f5790e0cf +Subproject commit f44a4f90867b49837da048f9055fdcd8a13c335b