diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
index 92c91491e..d36b504c5 100644
--- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
@@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
 openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
 openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
-yosys_args = -no_adder -family qlf_k4n8
+yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
index 824d92301..e3400e574 100644
--- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
@@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_vpr_circuit_format=eblif
-yosys_args = -no_adder -family qlf_k4n8
+yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
@@ -33,7 +33,8 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/c
 bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
 bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
 bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
-bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v
+#cavlc_top requires async reset/preset
+#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v
 bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
 # counter120bitx5 requires 5 clocks
 #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v
@@ -41,9 +42,12 @@ bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_
 bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v
 bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v
 bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v
-bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v
-bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v
-bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
+#i2c_master_top requires async reset/preset
+#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v
+#iir requires async reset/preset
+#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v
+#jpeg_qnr requires async reset/preset
+#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
 bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
 # sdc_controller requires 4 clocks
 #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
@@ -59,6 +63,7 @@ bench5_top = rs_decoder_top
 bench6_top = top_module
 bench7_top = sha256 
 bench8_top = cavlc_top
+#bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
 bench9_top = cf_fft_256_8
 #bench10_top = counter120bitx5
 #bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
@@ -67,8 +72,11 @@ bench12_top = dct_mac
 bench13_top = des_perf
 bench14_top = diffeq_f_systemC 
 bench15_top = i2c_master_top 
+#bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
 bench16_top = iir
+#bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
 bench17_top = jpeg_qnr
+#bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
 bench18_top = multi_enc_decx2x4 
 # sdc_controller requires 4 clocks
 #bench19_top = sdc_controller
diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
index 6f711649b..c00c2caed 100644
--- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
@@ -21,7 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
 openfpga_vpr_circuit_format=eblif
-yosys_args = -family qlf_k4n8
+yosys_args = -family qlf_k4n8 -no_ff_map
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
diff --git a/yosys b/yosys
index 3a9968de9..f44a4f908 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit 3a9968de914973f65928b724e889b134f8a4f2ae
+Subproject commit f44a4f90867b49837da048f9055fdcd8a13c335b