From 7f67794787f63d209fa41d087b11366343928267 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 10:54:40 -0700 Subject: [PATCH 01/10] [arch]add new arch to test --- ...lobal_nets_on_pins_example_script.openfpga | 2 +- .../config/pin_constraints_reset.xml | 7 + .../k4n4_rstOnLut_strong/config/task.conf | 43 + ...e_fracff_rstOnLut_registerable_io_40nm.xml | 735 ++++++++++++++++++ 4 files changed, 786 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml diff --git a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga index 9fff5a5d9..315816d04 100644 --- a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga @@ -30,7 +30,7 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation # Strongly recommend it is done after all the fix-up have been applied -repack --ignore_global_nets_on_pins clb.I[0:11] #--verbose +repack --ignore_global_nets_on_pins clb.I[0:11] --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINT_FILE} #--verbose # Build the bitstream # - Output the fabric-independent bitstream to a file diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml new file mode 100644 index 000000000..317f88671 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/pin_constraints_reset.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf new file mode 100644 index 000000000..61c992d3a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/task.conf @@ -0,0 +1,43 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = rst_on_lut +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml new file mode 100644 index 000000000..bd1ca8181 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml @@ -0,0 +1,735 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clk io.reset + io.outpad io.inpad io.clk io.reset + io.outpad io.inpad io.clk io.reset + io.outpad io.inpad io.clk io.reset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 7b7217d116c68500623d162ca0c2dc019937a49b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:08:51 -0700 Subject: [PATCH 02/10] [arch]add new arch to test --- ...racff_40nm_registerable_io_cc_openfpga.xml | 266 ++++++++++++++++++ 1 file changed, 266 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml new file mode 100644 index 000000000..3282f29db --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml @@ -0,0 +1,266 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 5cf315958d63ccaae83b0d7fa21971b2c172451d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:17:34 -0700 Subject: [PATCH 03/10] [test] deploy new test to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 288b8a277..47d7067f7 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -134,6 +134,7 @@ run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@ run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@ echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; run-task basic_tests/k4_series/k4n4_rstOnLut $@ +run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@ echo -e "Testing different tile organizations"; echo -e "Testing tiles with pins only on top and left sides"; From b0be27b384e8963cf15c4ae1bde6be4193876544 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:22:48 -0700 Subject: [PATCH 04/10] [test] add repack design constraints files --- .../k4n4_rstOnLut/config/repack_design_constraints.xml | 4 ++++ .../basic_tests/k4_series/k4n4_rstOnLut/config/task.conf | 1 + .../config/repack_design_constraints.xml | 5 +++++ 3 files changed, 10 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/repack_design_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf index ba2269805..dd6574e18 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut/config/task.conf @@ -19,6 +19,7 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/repack_design_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml new file mode 100644 index 000000000..9ed626423 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_rstOnLut_strong/config/repack_design_constraints.xml @@ -0,0 +1,5 @@ + + + + + From 32f48f16c72339705882294276646aee12a44858 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 11:54:58 -0700 Subject: [PATCH 05/10] [arch] fixed a few bugs --- ...eable_fracff_rstOnLut_registerable_io_40nm.xml | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml index bd1ca8181..049874bba 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_rstOnLut_registerable_io_40nm.xml @@ -238,9 +238,6 @@ - - - @@ -324,10 +321,14 @@ - + + + - + + + @@ -354,7 +355,9 @@ - + + + From 1c36ac28f19bc1784a740bda3652515d8e054222 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 12:17:32 -0700 Subject: [PATCH 06/10] [arch] code format --- .../k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml | 1 - 1 file changed, 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml index 3282f29db..8a05bacc2 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml @@ -223,7 +223,6 @@ - From 31da9bf6eacf0524bd2b08597eeefcfc1a532c74 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 15:10:25 -0700 Subject: [PATCH 07/10] [engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node --- openfpga/src/repack/repack.cpp | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 33c27937b..577dd00cd 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -258,7 +258,8 @@ static std::vector find_routed_pb_graph_pins_atom_net( * This function will find the actual routing traces of the demanded net * There is a specific search space applied when searching the routing traces: * - ONLY applicable to the pb_pin of top-level pb_graph_node - * - candidate can be limited to a set of pb pins + * - First-tier candidates are in the same port of the source pin + * - If nothing is found in first-tier, we find expand the range by considering all the pins in the same type that are available at the top-level pb_graph_node ***************************************************************************************/ static std::vector find_pb_route_by_atom_net( const t_pb* pb, const t_pb_graph_pin* source_pb_pin, @@ -267,6 +268,7 @@ static std::vector find_pb_route_by_atom_net( std::vector pb_route_indices; + std::vector candidate_pool; for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) { /* Bypass unused pins */ if ((0 == pb->pb_route.count(pin)) || @@ -277,12 +279,23 @@ static std::vector find_pb_route_by_atom_net( if (atom_net_id != pb->pb_route.at(pin).atom_net_id) { continue; } + candidate_pool.push_back(pin); + } + for (int pin : candidate_pool) { if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) { pb_route_indices.push_back(pin); } } + if (pb_route_indices.empty()) { + for (int pin : candidate_pool) { + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && source_pb_pin->port->type == pb->pb_route.at(pin).pb_graph_pin->port->type) { + pb_route_indices.push_back(pin); + } + } + } + return pb_route_indices; } @@ -662,9 +675,12 @@ static void add_lb_router_nets( if (0 == pb_route_indices.size()) { VTR_LOGV(verbose, "Bypass routing due to no routing traces found\n"); continue; - } else { - VTR_ASSERT(1 == pb_route_indices.size()); + } else if (1 == pb_route_indices.size()) { pb_route_index = pb_route_indices[0]; + } else { + VTR_LOG_ERROR("Found %d routing traces for net \'%s\' in clustered block \'%s\'. Expect only 1.\n", + pb_route_indices.size(), atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(), clustering_ctx.clb_nlist.block_name(block_id).c_str()); + VTR_ASSERT(1 == pb_route_indices.size()); } t_pb_graph_pin* packing_source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, pb_route_index); From 33e2b16cb1ca40384c1f66cab4978bf57f2b19ef Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 15:33:43 -0700 Subject: [PATCH 08/10] [arch] fixed a bug which caused verification failed --- .../k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml index 8a05bacc2..c2f043af5 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_registerable_io_cc_openfpga.xml @@ -202,9 +202,11 @@ + + From d1f3338837ef9bf9985b953da2dbd736d98f84b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 16:26:45 -0700 Subject: [PATCH 09/10] [engine] now repacker find only routable pins when given a net to search routing traces --- openfpga/src/repack/repack.cpp | 3 ++- openfpga/src/utils/pb_graph_utils.cpp | 24 ++++++++++++++++++++++++ openfpga/src/utils/pb_graph_utils.h | 2 ++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 577dd00cd..562a41f44 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -11,6 +11,7 @@ #include "build_physical_lb_rr_graph.h" #include "lb_router.h" #include "lb_router_utils.h" +#include "pb_graph_utils.h" #include "pb_type_utils.h" #include "physical_pb_utils.h" #include "repack.h" @@ -290,7 +291,7 @@ static std::vector find_pb_route_by_atom_net( if (pb_route_indices.empty()) { for (int pin : candidate_pool) { - if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && source_pb_pin->port->type == pb->pb_route.at(pin).pb_graph_pin->port->type) { + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && is_pb_graph_pins_share_interc(source_pb_pin, pb->pb_route.at(pin).pb_graph_pin)) { pb_route_indices.push_back(pin); } } diff --git a/openfpga/src/utils/pb_graph_utils.cpp b/openfpga/src/utils/pb_graph_utils.cpp index 4b80bd596..4746535fd 100644 --- a/openfpga/src/utils/pb_graph_utils.cpp +++ b/openfpga/src/utils/pb_graph_utils.cpp @@ -70,4 +70,28 @@ t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, return interc; } +/******************************************************************** + * This function identifies if two pb graph pins share at least one interconnect model + * The two pins should be in the same type of port, for example, both are inputs. + * Each pin may drive a number of outgoing edges while each edge represents different interconnect model + * By iterating over outgoing edges for each pin, common interconnect model may be found + *******************************************************************/ +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB) { + if (pinA->port->type != pinB->port->type) { + return false; + } + std::vector pinA_interc_list; + for (auto out_edge : pinA->output_edges) { + if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + pinA_interc_list.push_back(out_edge->interconnect); + } + } + for (auto out_edge : pinB->output_edges) { + if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + return true; + } + } + return false; +} + } /* end namespace openfpga */ diff --git a/openfpga/src/utils/pb_graph_utils.h b/openfpga/src/utils/pb_graph_utils.h index 209f87b9f..cbe2a096d 100644 --- a/openfpga/src/utils/pb_graph_utils.h +++ b/openfpga/src/utils/pb_graph_utils.h @@ -22,6 +22,8 @@ std::vector pb_graph_pin_inputs( t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, t_mode* selected_mode); +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB); + } /* end namespace openfpga */ #endif From 0af6c76239b87b079ecff36b1beb02617d59bfe1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Oct 2022 16:27:57 -0700 Subject: [PATCH 10/10] [engine] code format --- openfpga/src/repack/repack.cpp | 18 +++++++++++++----- openfpga/src/utils/pb_graph_utils.cpp | 22 ++++++++++++++-------- openfpga/src/utils/pb_graph_utils.h | 3 ++- 3 files changed, 29 insertions(+), 14 deletions(-) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 562a41f44..6dcc64a70 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -259,8 +259,10 @@ static std::vector find_routed_pb_graph_pins_atom_net( * This function will find the actual routing traces of the demanded net * There is a specific search space applied when searching the routing traces: * - ONLY applicable to the pb_pin of top-level pb_graph_node - * - First-tier candidates are in the same port of the source pin - * - If nothing is found in first-tier, we find expand the range by considering all the pins in the same type that are available at the top-level pb_graph_node + * - First-tier candidates are in the same port of the source pin + * - If nothing is found in first-tier, we find expand the range by considering + *all the pins in the same type that are available at the top-level + *pb_graph_node ***************************************************************************************/ static std::vector find_pb_route_by_atom_net( const t_pb* pb, const t_pb_graph_pin* source_pb_pin, @@ -291,7 +293,9 @@ static std::vector find_pb_route_by_atom_net( if (pb_route_indices.empty()) { for (int pin : candidate_pool) { - if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && is_pb_graph_pins_share_interc(source_pb_pin, pb->pb_route.at(pin).pb_graph_pin)) { + if (pb->pb_route.at(pin).pb_graph_pin->parent_node->is_root() && + is_pb_graph_pins_share_interc(source_pb_pin, + pb->pb_route.at(pin).pb_graph_pin)) { pb_route_indices.push_back(pin); } } @@ -679,8 +683,12 @@ static void add_lb_router_nets( } else if (1 == pb_route_indices.size()) { pb_route_index = pb_route_indices[0]; } else { - VTR_LOG_ERROR("Found %d routing traces for net \'%s\' in clustered block \'%s\'. Expect only 1.\n", - pb_route_indices.size(), atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(), clustering_ctx.clb_nlist.block_name(block_id).c_str()); + VTR_LOG_ERROR( + "Found %d routing traces for net \'%s\' in clustered block \'%s\'. " + "Expect only 1.\n", + pb_route_indices.size(), + atom_ctx.nlist.net_name(atom_net_id_to_route).c_str(), + clustering_ctx.clb_nlist.block_name(block_id).c_str()); VTR_ASSERT(1 == pb_route_indices.size()); } t_pb_graph_pin* packing_source_pb_pin = diff --git a/openfpga/src/utils/pb_graph_utils.cpp b/openfpga/src/utils/pb_graph_utils.cpp index 4746535fd..5187bbaac 100644 --- a/openfpga/src/utils/pb_graph_utils.cpp +++ b/openfpga/src/utils/pb_graph_utils.cpp @@ -71,23 +71,29 @@ t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, } /******************************************************************** - * This function identifies if two pb graph pins share at least one interconnect model - * The two pins should be in the same type of port, for example, both are inputs. - * Each pin may drive a number of outgoing edges while each edge represents different interconnect model - * By iterating over outgoing edges for each pin, common interconnect model may be found + * This function identifies if two pb graph pins share at least one interconnect + *model The two pins should be in the same type of port, for example, both are + *inputs. Each pin may drive a number of outgoing edges while each edge + *represents different interconnect model By iterating over outgoing edges for + *each pin, common interconnect model may be found *******************************************************************/ -bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB) { +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, + const t_pb_graph_pin* pinB) { if (pinA->port->type != pinB->port->type) { return false; } std::vector pinA_interc_list; for (auto out_edge : pinA->output_edges) { - if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + if (pinA_interc_list.end() == std::find(pinA_interc_list.begin(), + pinA_interc_list.end(), + out_edge->interconnect)) { pinA_interc_list.push_back(out_edge->interconnect); } - } + } for (auto out_edge : pinB->output_edges) { - if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(), pinA_interc_list.end(), out_edge->interconnect)) { + if (pinA_interc_list.end() != std::find(pinA_interc_list.begin(), + pinA_interc_list.end(), + out_edge->interconnect)) { return true; } } diff --git a/openfpga/src/utils/pb_graph_utils.h b/openfpga/src/utils/pb_graph_utils.h index cbe2a096d..e340ba860 100644 --- a/openfpga/src/utils/pb_graph_utils.h +++ b/openfpga/src/utils/pb_graph_utils.h @@ -22,7 +22,8 @@ std::vector pb_graph_pin_inputs( t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin, t_mode* selected_mode); -bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, const t_pb_graph_pin* pinB); +bool is_pb_graph_pins_share_interc(const t_pb_graph_pin* pinA, + const t_pb_graph_pin* pinB); } /* end namespace openfpga */