[lib] typo
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@ -61,7 +61,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp,
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}
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case ClockNetwork::e_tap_type::REGION: {
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openfpga::write_tab_to_file(fp, 4);
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fp << "<" << XML_CLOCK_TREE_TAP_SINGLE_NODE_NAME << "";
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fp << "<" << XML_CLOCK_TREE_TAP_REGION_NODE_NAME << "";
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write_xml_attribute(
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fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_FROM_PIN,
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clk_ntwk.tap_from_port(tap_id).to_verilog_string().c_str());
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