diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
index e3e74a409..347359d53 100644
--- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml
index d015287fb..b02721d7a 100644
--- a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml
@@ -54,7 +54,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
 DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
 DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
 DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
-DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
 
 MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
 MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml
index 4d1136b15..985f9eb5b 100644
--- a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml
+++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml
@@ -37,7 +37,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
 DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
 DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
 DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
-DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
 
 MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
 MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12