diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp index 569b9127f..b246c02e1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp @@ -162,6 +162,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp, * See more details in the function print_verilog_mux_local_decoder() for more details ***************************************************************************************/ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, + std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, @@ -222,8 +223,9 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, /* Close the file stream */ fp.close(); - /* Add fname to the linked list when debugging is finished */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } /*************************************************************************************** diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h index 8f4a52816..418b4a4ae 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.h @@ -9,13 +9,16 @@ /* Include other header files which are dependency on the function declared below */ #include #include +#include +#include "vpr_types.h" #include "circuit_library.h" #include "mux_graph.h" #include "mux_library.h" #include "module_manager.h" void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, + std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 5f116f4a0..fc353f725 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -525,6 +525,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager * etc. ***********************************************/ void print_verilog_submodule_essentials(ModuleManager& module_manager, + std::vector& netlist_names, const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { @@ -575,8 +576,6 @@ void print_verilog_submodule_essentials(ModuleManager& module_manager, /* Close file handler*/ fp.close(); - /* Add fname to the linked list */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); - - return; + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h index bbdd60b69..6431d0390 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.h @@ -13,6 +13,7 @@ #include "circuit_library.h" void print_verilog_submodule_essentials(ModuleManager& module_manager, + std::vector& netlist_names, const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index fb1cdc75f..5544c92f9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -183,6 +183,7 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, *****************************************************************************/ static void print_verilog_grid(ModuleManager& module_manager, + std::vector& netlist_names, const std::string& verilog_dir, const std::string& subckt_dir, t_type_ptr phy_block_type, @@ -261,8 +262,8 @@ void print_verilog_grid(ModuleManager& module_manager, /* Close file handler */ fp.close(); - /* Add fname to the linked list */ - grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str()); + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } /***************************************************************************** @@ -275,6 +276,9 @@ void print_verilog_grids(ModuleManager& module_manager, const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_mapping) { + /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ + std::vector netlist_names; + /* Enumerate the types, dump one Verilog module for each */ for (int itype = 0; itype < num_types; itype++) { if (EMPTY_TYPE == &type_descriptors[itype]) { @@ -284,7 +288,7 @@ void print_verilog_grids(ModuleManager& module_manager, /* Special for I/O block, generate one module for each border side */ for (int iside = 0; iside < NUM_SIDES; iside++) { Side side_manager(iside); - print_verilog_grid(module_manager, + print_verilog_grid(module_manager, netlist_names, verilog_dir, subckt_dir, &type_descriptors[itype], side_manager.get_side(), @@ -293,7 +297,7 @@ void print_verilog_grids(ModuleManager& module_manager, continue; } else if (FILL_TYPE == &type_descriptors[itype]) { /* For CLB */ - print_verilog_grid(module_manager, + print_verilog_grid(module_manager, netlist_names, verilog_dir, subckt_dir, &type_descriptors[itype], NUM_SIDES, @@ -301,7 +305,7 @@ void print_verilog_grids(ModuleManager& module_manager, continue; } else { /* For heterogenenous blocks */ - print_verilog_grid(module_manager, + print_verilog_grid(module_manager, netlist_names, verilog_dir, subckt_dir, &type_descriptors[itype], NUM_SIDES, @@ -312,10 +316,8 @@ void print_verilog_grids(ModuleManager& module_manager, /* Output a header file for all the logic blocks */ vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n"); std::string grid_verilog_fname(logic_block_verilog_file_name); - /* TODO: remove .bak when it is ready */ - //grid_verilog_fname += ".bak"; - dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head, - subckt_dir.c_str(), - grid_verilog_fname.c_str()); + print_verilog_netlist_include_header_file(netlist_names, + subckt_dir.c_str(), + grid_verilog_fname.c_str()); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp index 08fd812a8..53126cec6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.cpp @@ -29,13 +29,12 @@ * in the circuit library ********************************************************************/ void print_verilog_submodule_luts(ModuleManager& module_manager, + std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map) { - /* TODO: remove .bak when this part is completed and tested */ std::string verilog_fname = submodule_dir + luts_verilog_file_name; - //verilog_fname +=".bak"; std::fstream fp; @@ -70,7 +69,7 @@ void print_verilog_submodule_luts(ModuleManager& module_manager, /* Close the file handler */ fp.close(); - /* Add fname to the linked list */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h index 6eee42b61..f546b400f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_lut.h @@ -13,6 +13,7 @@ #include "module_manager.h" void print_verilog_submodule_luts(ModuleManager& module_manager, + std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp index 31ac06cac..ea7cd8498 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.cpp @@ -97,6 +97,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, * memory-bank organization for the memories. ********************************************************************/ void print_verilog_submodule_memories(ModuleManager& module_manager, + std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, @@ -104,7 +105,6 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, const bool& use_explicit_port_map) { /* Plug in with the mux subckt */ std::string verilog_fname(submodule_dir + memories_verilog_file_name); - //verilog_fname += ".bak"; /* Create the file stream */ std::fstream fp; @@ -187,7 +187,7 @@ void print_verilog_submodule_memories(ModuleManager& module_manager, /* Close the file stream */ fp.close(); - /* Add fname to the linked list */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h index bfba1c391..29387fccc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_memory.h @@ -14,6 +14,7 @@ #include "module_manager.h" void print_verilog_submodule_memories(ModuleManager& module_manager, + std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp index caa8c1a00..f13c82f33 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.cpp @@ -1218,6 +1218,7 @@ void generate_verilog_mux_module(ModuleManager& module_manager, * multiplexers in the FPGA device **********************************************/ void print_verilog_submodule_muxes(ModuleManager& module_manager, + std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, t_sram_orgz_info* cur_sram_orgz_info, @@ -1279,7 +1280,7 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, try_update_sram_orgz_info_reserved_blwl(cur_sram_orgz_info, mux_lib.max_mux_size(), mux_lib.max_mux_size()); - /* Add fname to the linked list when debugging is finished */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h index 51f3c7d7b..604e246e8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_mux.h @@ -7,6 +7,7 @@ /* Include other header files which are dependency on the function declared below */ #include +#include #include "circuit_library.h" #include "mux_graph.h" @@ -14,6 +15,7 @@ #include "module_manager.h" void print_verilog_submodule_muxes(ModuleManager& module_manager, + std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp index c392f699f..9391a588f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.cpp @@ -72,6 +72,7 @@ ********************************************************************/ static void print_verilog_routing_connection_box_unique_module(ModuleManager& module_manager, + std::vector& netlist_names, const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, @@ -107,8 +108,8 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma /* Close file handler */ fp.close(); - /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } /********************************************************************* @@ -176,6 +177,7 @@ void print_verilog_routing_connection_box_unique_module(ModuleManager& module_ma ********************************************************************/ static void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manager, + std::vector& netlist_names, const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, @@ -207,19 +209,17 @@ void print_verilog_routing_switch_box_unique_module(ModuleManager& module_manage /* Close file handler */ fp.close(); - /* Add fname to the linked list */ - routing_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(routing_verilog_subckt_file_path_head, verilog_fname.c_str()); - - return; + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } - /******************************************************************** * Iterate over all the connection blocks in a device * and build a module for each of them *******************************************************************/ static void print_verilog_flatten_connection_block_modules(ModuleManager& module_manager, + std::vector& netlist_names, const DeviceRRGSB& L_device_rr_gsb, const std::string& verilog_dir, const std::string& subckt_dir, @@ -239,7 +239,7 @@ void print_verilog_flatten_connection_block_modules(ModuleManager& module_manage || (true != rr_gsb.is_cb_exist(cb_type))) { continue; } - print_verilog_routing_connection_box_unique_module(module_manager, + print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, verilog_dir, subckt_dir, rr_gsb, cb_type, @@ -266,6 +266,9 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager, /* We only support uni-directional routing architecture now */ VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); + /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ + std::vector netlist_names; + /* TODO: deprecate DeviceCoordinator, use vtr::Point only! */ DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range(); @@ -273,7 +276,7 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager, for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy); - print_verilog_routing_switch_box_unique_module(module_manager, + print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, verilog_dir, subckt_dir, rr_gsb, @@ -281,14 +284,14 @@ void print_verilog_flatten_routing_modules(ModuleManager& module_manager, } } - print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(module_manager, netlist_names, L_device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); - print_verilog_flatten_connection_block_modules(module_manager, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(module_manager, netlist_names, L_device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); - dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head, - subckt_dir.c_str(), - routing_verilog_file_name); + print_verilog_netlist_include_header_file(netlist_names, + subckt_dir.c_str(), + routing_verilog_file_name); } @@ -311,10 +314,13 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager, /* We only support uni-directional routing architecture now */ VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); + /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ + std::vector netlist_names; + /* Build unique switch block modules */ for (size_t isb = 0; isb < L_device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(isb); - print_verilog_routing_switch_box_unique_module(module_manager, + print_verilog_routing_switch_box_unique_module(module_manager, netlist_names, verilog_dir, subckt_dir, unique_mirror, @@ -325,7 +331,7 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager, for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANX, icb); - print_verilog_routing_connection_box_unique_module(module_manager, + print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, verilog_dir, subckt_dir, unique_mirror, CHANX, @@ -336,7 +342,7 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager, for (size_t icb = 0; icb < L_device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { const RRGSB& unique_mirror = L_device_rr_gsb.get_cb_unique_module(CHANY, icb); - print_verilog_routing_connection_box_unique_module(module_manager, + print_verilog_routing_connection_box_unique_module(module_manager, netlist_names, verilog_dir, subckt_dir, unique_mirror, CHANY, @@ -344,8 +350,7 @@ void print_verilog_unique_routing_modules(ModuleManager& module_manager, } vpr_printf(TIO_MESSAGE_INFO,"Generating header file for routing submodules...\n"); - dump_verilog_subckt_header_file(routing_verilog_subckt_file_path_head, - subckt_dir.c_str(), - routing_verilog_file_name); - + print_verilog_netlist_include_header_file(netlist_names, + subckt_dir.c_str(), + routing_verilog_file_name); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp index eaeb0115a..7169ce491 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.cpp @@ -8,8 +8,6 @@ #include "util.h" /* FPGA-Verilog header files */ -#include "verilog_global.h" -#include "verilog_utils.h" #include "verilog_submodule_utils.h" #include "verilog_essential_gates.h" #include "verilog_decoders.h" @@ -17,6 +15,7 @@ #include "verilog_lut.h" #include "verilog_wire.h" #include "verilog_memory.h" +#include "verilog_writer_utils.h" /* Header file for this source file */ #include "verilog_submodules.h" @@ -45,9 +44,13 @@ void print_verilog_submodules(ModuleManager& module_manager, vpr_printf(TIO_MESSAGE_INFO, "Registering user-defined modules...\n"); + /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ + std::vector netlist_names; + add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib); print_verilog_submodule_essentials(module_manager, + netlist_names, std::string(verilog_dir), std::string(submodule_dir), Arch.spice->circuit_lib); @@ -59,9 +62,10 @@ void print_verilog_submodules(ModuleManager& module_manager, /* NOTE: local decoders generation must go before the MUX generation!!! * because local decoders modules will be instanciated in the MUX modules */ - print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, + print_verilog_submodule_mux_local_decoders(module_manager, netlist_names, + mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); - print_verilog_submodule_muxes(module_manager, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, + print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info, std::string(verilog_dir), std::string(submodule_dir), fpga_verilog_opts.dump_explicit_verilog); @@ -69,16 +73,17 @@ void print_verilog_submodules(ModuleManager& module_manager, /* LUTes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules for LUTs...\n"); - print_verilog_submodule_luts(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir), + print_verilog_submodule_luts(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir), fpga_verilog_opts.dump_explicit_verilog); /* Hard wires */ - print_verilog_submodule_wires(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); + print_verilog_submodule_wires(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir)); /* 4. Memories */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules for configuration memory blocks...\n"); - print_verilog_submodule_memories(module_manager, mux_lib, Arch.spice->circuit_lib, + print_verilog_submodule_memories(module_manager, netlist_names, + mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir), fpga_verilog_opts.dump_explicit_verilog); @@ -89,9 +94,9 @@ void print_verilog_submodules(ModuleManager& module_manager, /* Create a header file to include all the subckts */ vpr_printf(TIO_MESSAGE_INFO, - "Generating header file for basic submodules...\n"); - dump_verilog_subckt_header_file(submodule_verilog_subckt_file_path_head, - submodule_dir, - submodule_verilog_file_name); + "Generating header file for primitive modules...\n"); + print_verilog_netlist_include_header_file(netlist_names, + submodule_dir, + submodule_verilog_file_name); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp index 6c52c6e84..41dc33bcb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.cpp @@ -93,6 +93,7 @@ void print_verilog_wire_module(ModuleManager& module_manager, * Top-level function to print wire modules *******************************************************************/ void print_verilog_submodule_wires(ModuleManager& module_manager, + std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir) { @@ -127,6 +128,6 @@ void print_verilog_submodule_wires(ModuleManager& module_manager, /* Close the file stream */ fp.close(); - /* Add fname to the linked list */ - submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); + /* Add fname to the netlist name list */ + netlist_names.push_back(verilog_fname); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h index e45cf483a..a5a29f2be 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h @@ -15,6 +15,7 @@ #include "module_manager.h" void print_verilog_submodule_wires(ModuleManager& module_manager, + std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, const std::string& submodule_dir); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index 41766444b..4d892f05f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -1367,3 +1367,29 @@ void print_verilog_clock_stimuli(std::fstream& fp, fp << std::endl; } +/******************************************************************** + * Output a header file that includes a number of Verilog netlists + * so that it can be easily included in a top-level netlist + ********************************************************************/ +void print_verilog_netlist_include_header_file(const std::vector& netlists_to_be_included, + const char* subckt_dir, + const char* header_file_name) { + std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name)); + + /* Create the file stream */ + std::fstream fp; + fp.open(verilog_fname, std::fstream::out | std::fstream::trunc); + + check_file_handler(fp); + + /* Generate the descriptions*/ + print_verilog_file_header(fp, "Header file to include other Verilog netlists"); + + /* Output file names */ + for (const std::string& netlist_name : netlists_to_be_included) { + fp << "`include \"" << netlist_name << "\"" << std::endl; + } + + /* close file stream */ + fp.close(); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 977ae037b..c2aaf1b38 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -168,4 +168,8 @@ void print_verilog_clock_stimuli(std::fstream& fp, const float& pulse_width, const std::string& wait_condition); +void print_verilog_netlist_include_header_file(const std::vector& netlists_to_be_included, + const char* subckt_dir, + const char* header_file_name); + #endif