From 72d2fc6d69eb86cb1adf0c89edda9986f3593d18 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 25 Dec 2019 20:24:41 -0700 Subject: [PATCH] add entry to new functions for pin duplication --- .../module_builder/build_device_module.cpp | 3 +- .../build_grid_module_duplicated_pins.cpp | 51 +++++++++++++++++++ .../build_grid_module_duplicated_pins.h | 20 ++++++++ .../module_builder/build_grid_modules.cpp | 46 ++++++++++++----- .../module_builder/build_grid_modules.h | 3 +- 5 files changed, 108 insertions(+), 15 deletions(-) create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp create mode 100644 vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.h diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp index 83a387338..0f7ab96e3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_module.cpp @@ -105,7 +105,8 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup, /* Build grid and programmable block modules */ build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib, - arch.sram_inf.verilog_sram_inf_orgz->type, sram_model); + arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, + TRUE == vpr_setup.FPGA_SPICE_Opts.duplicate_grid_pin); if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) { build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp new file mode 100644 index 000000000..d94ea2c00 --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.cpp @@ -0,0 +1,51 @@ +/******************************************************************** + * This file includes functions that are used to add duplicated + * pins to each side of a grid + * + * These functions are located in this file, being separated from + * the default functions in build_grid_module.cpp + * This allows us to keep new features easy to be maintained. + * + * Please follow this rules when creating new features! + *******************************************************************/ +#include "build_grid_module_duplicated_pins.h" + +/******************************************************************** + * This function adds pb_type ports to top-level grid module with duplication + * For each pin at each side, we create two pins which are short-wired + * They are driven by the same pin, e.g., pinA in the child module + * But in this top module, we will create two pins, each of which indicates + * the physical location of pin. + * Take the following example: + * One is called pinA_upper which is located close to the top side of this grid + * The other is called pinA_lower which is located close to the bottom side of this grid + * + * Similarly, we duplicate pins at TOP, RIGHT, BOTTOM and LEFT sides. + * For LEFT side, upper and lower pins carry the indication in physical location as RIGHT side. + * For TOP and BOTTOM side, upper pin is located close to the left side of a grid, while lower + * pin is located close to the right side of a grid + * + * pinB_upper pinB_lower + * ^ ^ + * | | + * ---------------+ + * |--->pinA_upper + * | + * Grid | + * | + * |--->pinA_lower + * ---------------+ + *******************************************************************/ +void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + t_type_ptr grid_type_descriptor, + const e_side& border_side) { +} + +void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + const ModuleId& child_module, + const size_t& child_instance, + t_type_ptr grid_type_descriptor, + const e_side& border_side) { +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.h new file mode 100644 index 000000000..feaca16fd --- /dev/null +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_module_duplicated_pins.h @@ -0,0 +1,20 @@ +#ifndef BUILD_GRID_MODULE_DUPLICATED_PINS_H +#define BUILD_GRID_MODULE_DUPLICATED_PINS_H + +#include "module_manager.h" +#include "sides.h" +#include "vpr_types.h" + +void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + t_type_ptr grid_type_descriptor, + const e_side& border_side); + +void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager, + const ModuleId& grid_module, + const ModuleId& child_module, + const size_t& child_instance, + t_type_ptr grid_type_descriptor, + const e_side& border_side); + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 592281400..ba913fe4f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -27,6 +27,7 @@ /* Header files for Verilog generator */ #include "verilog_global.h" +#include "build_grid_module_duplicated_pins.h" #include "build_grid_modules.h" /******************************************************************** @@ -1003,7 +1004,8 @@ void build_grid_module(ModuleManager& module_manager, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, t_type_ptr phy_block_type, - const e_side& border_side) { + const e_side& border_side, + const bool& duplicate_grid_pin) { /* Check code: if this is an IO block, the border side MUST be valid */ if (IO_TYPE == phy_block_type) { VTR_ASSERT(NUM_SIDES != border_side); @@ -1053,14 +1055,28 @@ void build_grid_module(ModuleManager& module_manager, } /* Add grid ports(pins) to the module */ - add_grid_module_pb_type_ports(module_manager, grid_module, - phy_block_type, border_side); - - /* Add module nets to connect the pb_type ports to sub modules */ - for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { - add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, - pb_module, child_instance, - phy_block_type, border_side); + if (false == duplicate_grid_pin) { + /* Default way to add these ports by following the definition in pb_types */ + add_grid_module_pb_type_ports(module_manager, grid_module, + phy_block_type, border_side); + /* Add module nets to connect the pb_type ports to sub modules */ + for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { + add_grid_module_nets_connect_pb_type_ports(module_manager, grid_module, + pb_module, child_instance, + phy_block_type, border_side); + } + } else { + VTR_ASSERT_SAFE(true == duplicate_grid_pin); + /* TODO: Add these ports with duplication */ + add_grid_module_duplicated_pb_type_ports(module_manager, grid_module, + phy_block_type, border_side); + + /* TODO: Add module nets to connect the duplicated pb_type ports to sub modules */ + for (const size_t& child_instance : module_manager.child_module_instances(grid_module, pb_module)) { + add_grid_module_nets_connect_duplicated_pb_type_ports(module_manager, grid_module, + pb_module, child_instance, + phy_block_type, border_side); + } } /* Add global ports to the pb_module: @@ -1112,7 +1128,8 @@ void build_grid_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model) { + const CircuitModelId& sram_model, + const bool& duplicate_grid_pin) { /* Start time count */ clock_t t_start = clock(); @@ -1131,7 +1148,8 @@ void build_grid_modules(ModuleManager& module_manager, build_grid_module(module_manager, mux_lib, circuit_lib, sram_orgz_type, sram_model, &type_descriptors[itype], - side_manager.get_side()); + side_manager.get_side(), + duplicate_grid_pin); } continue; } else if (FILL_TYPE == &type_descriptors[itype]) { @@ -1139,14 +1157,16 @@ void build_grid_modules(ModuleManager& module_manager, build_grid_module(module_manager, mux_lib, circuit_lib, sram_orgz_type, sram_model, &type_descriptors[itype], - NUM_SIDES); + NUM_SIDES, + duplicate_grid_pin); continue; } else { /* For heterogenenous blocks */ build_grid_module(module_manager, mux_lib, circuit_lib, sram_orgz_type, sram_model, &type_descriptors[itype], - NUM_SIDES); + NUM_SIDES, + duplicate_grid_pin); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h index ad1880e1c..b7c6d2ac5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h @@ -13,6 +13,7 @@ void build_grid_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const e_sram_orgz& sram_orgz_type, - const CircuitModelId& sram_model); + const CircuitModelId& sram_model, + const bool& duplicate_grid_pin); #endif