diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp
index f743ef3f6..2e16058c0 100644
--- a/openfpga/src/base/openfpga_naming.cpp
+++ b/openfpga/src/base/openfpga_naming.cpp
@@ -1445,4 +1445,14 @@ std::string generate_const_value_module_output_port_name(const size_t& const_val
   return generate_const_value_module_name(const_val);
 }
 
+/*********************************************************************
+ * Generate the analysis SDC file name
+ * The format is
+ *   <circuit_name>_<postfix>
+ ********************************************************************/
+std::string generate_analysis_sdc_file_name(const std::string& circuit_name,
+                                            const std::string& file_name_postfix) {
+  return circuit_name + "_" + file_name_postfix;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h
index 3f374b8e5..a43fe8bb0 100644
--- a/openfpga/src/base/openfpga_naming.h
+++ b/openfpga/src/base/openfpga_naming.h
@@ -264,6 +264,9 @@ std::string generate_const_value_module_name(const size_t& const_val);
 
 std::string generate_const_value_module_output_port_name(const size_t& const_val);
 
+std::string generate_analysis_sdc_file_name(const std::string& circuit_name,
+                                            const std::string& file_name_postfix);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index a4730cae6..ae145110b 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -228,7 +228,7 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
                         const std::vector<CircuitPortId>& global_ports,
                         const bool& compact_routing_hierarchy) {
   /* Create the file name for Verilog netlist */
-  std::string sdc_fname(option.sdc_dir() + std::string(SDC_ANALYSIS_FILE_NAME));
+  std::string sdc_fname(option.sdc_dir() + generate_analysis_sdc_file_name(vpr_ctx.atom().nlist.netlist_name(), std::string(SDC_ANALYSIS_FILE_NAME)));
 
   std::string timer_message = std::string("Generating SDC for Timing/Power analysis on the mapped FPGA '")
                             + sdc_fname