From 71e0026a50e086393f8365770c4cabfd44b48081 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 22 Feb 2021 11:32:17 -0700
Subject: [PATCH] [Test] Add new test for 5-clock counter to quicklogic tests

---
 .../config/pin_constraints.xml                | 11 +++++
 .../config/repack_pin_constraints.xml         | 14 +++++++
 .../counter_5clock_test/config/task.conf      | 40 +++++++++++++++++++
 3 files changed, 65 insertions(+)
 create mode 100644 openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
 create mode 100644 openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
 create mode 100644 openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf

diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
new file mode 100644
index 000000000..e6949c9d4
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
@@ -0,0 +1,11 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the clk0 signal to the clk[0] port of the FPGA fabric
+       - the clk1 signal to the clk[1] port of the FPGA fabric
+    -->
+  <set_io pin="clk[0]" net="clk0"/>
+  <set_io pin="clk[1]" net="clk1"/>
+  <set_io pin="clk[2]" net="OPEN"/>
+  <set_io pin="clk[3]" net="OPEN"/>
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
new file mode 100644
index 000000000..d695cf85e
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
@@ -0,0 +1,14 @@
+<repack_design_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
+       - the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
+       and ensure no signals could be mapped to 
+       - the clk[2] port of all the clb tiles available in the FPGA fabric
+       - the clk[3] port of all the clb tiles available in the FPGA fabric
+    -->
+  <pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/>
+  <pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/>
+  <pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
+  <pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
+</repack_design_constraints>
+
diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
new file mode 100644
index 000000000..417a53085
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
@@ -0,0 +1,40 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+# Due to the limitation in ACE2 which cannot output .blif files 
+# with correct multi-clock assignments to .latch lines
+# We have to use the vpr_blif flow where the .blif is modified
+# based on yosys outputs with correct clock assignment!
+# TODO: This limitation should be removed and we should use yosys_vpr flow!!!
+#fpga_flow=vpr_blif
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
+openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter5clock_test/config/repack_pin_constraints.xml
+openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v
+
+[SYNTHESIS_PARAM]
+bench0_top = counter120bitx5
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]