From 71b0b171b47c223192b190e1d62fc19ec9abc47d Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Fri, 17 Dec 2021 05:11:35 -0800 Subject: [PATCH] disable nolatch option for k6n10f family for now --- openfpga_flow/scripts/run_fpga_flow.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index bb44f2f40..f49ee0f6f 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -99,6 +99,8 @@ parser.add_argument('--arch_variable_file', type=str, default=None, # help="Key file for shell") parser.add_argument('--yosys_tmpl', type=str, default=None, help="Alternate yosys template, generates top_module.blif") +parser.add_argument('--yosys_args', type=str, default=None, + help="Arguments for yosys") parser.add_argument('--ys_rewrite_tmpl', type=str, default=None, help="Alternate yosys template, to rewrite verilog netlist") parser.add_argument('--verific', action="store_true", @@ -487,11 +489,22 @@ def create_yosys_params(): tmpVar = OpenFPGAArgs[indx][2:].upper() ys_params[tmpVar] = OpenFPGAArgs[indx+1] + yosys_args = [] + if args.yosys_args: + yosys_args = ys_params["YOSYS_ARGS"].split() + yosysargparser = argparse.ArgumentParser(description="Parses yosys arguments") + yosysargparser.add_argument("-family", type=str, help="Family") + yosys_args = yosysargparser.parse_args(yosys_args) + if not args.verific: + if args.yosys_args and yosys_args.family == "qlf_k6n10f": ys_params["READ_VERILOG_FILE"] = " \n".join([ - #"read_verilog -nolatches " + shlex.quote(eachfile) "read_verilog " + shlex.quote(eachfile) for eachfile in args.benchmark_files]) + else: + ys_params["READ_VERILOG_FILE"] = " \n".join([ + "read_verilog -nolatches " + shlex.quote(eachfile) + for eachfile in args.benchmark_files]) else: if "ADD_INCLUDE_DIR" not in ys_params: ys_params["ADD_INCLUDE_DIR"] = ""