Merge branch 'master' into vtr_upgrade

VERSION.md

@@ -1 +1 @@
-1.1.422
+1.1.437

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -115,6 +115,31 @@ write_gsb_to_xml
 
     Only output unique GSBs to XML files
 
+  .. option:: --exclude_rr_info
+
+    Exclude routing resource graph information from output files, e.g., node id as well as other attributes. This is useful to check the connection inside GSBs purely.
+
+  .. option:: --exclude <string>
+
+    Exclude part of the GSB data to be outputted. Can be [``sb``|``cbx``|``cby``]. Users can exclude multiple parts by using a splitter ``,``.
+    For example, 
+
+      - ``--exclude sb``
+      - ``--exclude sb,cbx``
+
+  .. option:: --gsb_names <string>
+
+    Specify the name of GSB to be outputted. Users can specify multiple GSBs by using a splitter ``,``.
+    When specified, only the GSBs whose names match the list will be outputted to files.
+    If not specified, all the GSBs will be outputted.
+
+    .. note:: When option ``--unique`` is enable, the given name of GSBs should match the unique modules! 
+
+    For example,
+
+      - ``--gsb_names gsb_2__4_,gsb_3__2_``
+      - ``--gsb_names gsb_2__4_``
+
   .. option:: --verbose
 
     Show verbose log

openfpga/src/annotation/rr_gsb_writer_option.cpp

@@ -0,0 +1,122 @@
+/******************************************************************************
+ * Memember functions for data structure RRGSBWriterOption
+ ******************************************************************************/
+#include <map>
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+#include "rr_gsb_writer_option.h"
+#include "openfpga_tokenizer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Constructors
+ *************************************************/
+RRGSBWriterOption::RRGSBWriterOption() {
+  output_directory_.clear();
+  unique_module_only_ = false;
+  exclude_content_ = {false, false, false, false};
+  include_gsb_names_.clear();
+  verbose_output_ = false;
+  num_parse_errors_ = 0;
+}
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+std::string RRGSBWriterOption::output_directory() const {
+  return output_directory_;
+}
+
+bool RRGSBWriterOption::unique_module_only() const {
+  return unique_module_only_;
+}
+
+bool RRGSBWriterOption::include_rr_info() const {
+  return !exclude_content_[0];
+}
+
+bool RRGSBWriterOption::include_cb_content(const t_rr_type& cb_type) const {
+  if (cb_type == CHANX) {
+    return !exclude_content_[1];
+  }
+  VTR_ASSERT(cb_type == CHANY);
+  return !exclude_content_[2];
+}
+
+bool RRGSBWriterOption::include_sb_content() const {
+  return !exclude_content_[3];
+}
+
+std::vector<std::string> RRGSBWriterOption::include_gsb_names() const {
+  return include_gsb_names_;
+}
+
+bool RRGSBWriterOption::verbose_output() const {
+  return verbose_output_;
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+void RRGSBWriterOption::set_output_directory(const std::string& output_dir) {
+  output_directory_ = output_dir;
+}
+
+void RRGSBWriterOption::set_unique_module_only(const bool& enabled) {
+  unique_module_only_ = enabled;
+}
+
+void RRGSBWriterOption::set_exclude_rr_info(const bool& enabled) {
+  exclude_content_[0] = enabled;
+}
+
+void RRGSBWriterOption::set_exclude_content(const std::string& content) {
+  num_parse_errors_ = 0;
+  /* Split the content using a tokenizer */
+  StringToken tokenizer(content);
+  std::vector<std::string> tokens = tokenizer.split(',');
+  /* Parse each token */
+  std::map<std::string, int> token2index = { {"sb", 3}, {"cbx", 1}, {"cby", 2} };
+  for (std::string token : tokens) {
+    auto result = token2index.find(token);
+    if (result == token2index.end()) {
+      /* Cannot find a valid keyword, error out */
+      std::string keyword_list;
+      for (auto pair : token2index) {
+        keyword_list += pair.first + "|";
+      }
+      keyword_list.pop_back();
+      std::string err_msg = std::string("Invalid content '") + token + std::string("' to skip, expect [ ") + keyword_list + std::string(" ]");
+      VTR_LOG_ERROR(err_msg.c_str());
+      num_parse_errors_++;
+      continue;
+    }
+    /* Now we should have a valid keyword, assign to designated flag */
+    exclude_content_[result->second] = true;
+  }
+}
+
+void RRGSBWriterOption::set_include_gsb_names(const std::string& content) {
+  /* Split the content using a tokenizer */
+  StringToken tokenizer(content);
+  include_gsb_names_ = tokenizer.split(',');
+}
+
+void RRGSBWriterOption::set_verbose_output(const bool& enabled) {
+  verbose_output_ = enabled;
+}
+
+bool RRGSBWriterOption::valid() const {
+  if (output_directory_.empty()) {
+    return false;
+  } 
+  if (num_parse_errors_) {
+    return false;
+  }
+  return true;
+}
+
+} /* end namespace openfpga */

openfpga/src/annotation/rr_gsb_writer_option.h

@@ -0,0 +1,67 @@
+#ifndef RR_GSB_WRITER_OPTION_H
+#define RR_GSB_WRITER_OPTION_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+#include <string>
+#include <vector>
+#include "rr_graph_types.h"
+
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Options for RRGSB writer
+ *******************************************************************/
+class RRGSBWriterOption {
+  public: /* Public constructor */
+    /* Set default options */
+    RRGSBWriterOption();
+  public: /* Public accessors */
+    std::string output_directory() const;
+    bool unique_module_only() const;
+    bool include_rr_info() const;
+    bool include_cb_content(const t_rr_type& cb_type) const;
+    bool include_sb_content() const;
+    std::vector<std::string> include_gsb_names() const;
+    bool verbose_output() const;
+  public: /* Public mutators */
+    void set_output_directory(const std::string& output_dir);
+    void set_unique_module_only(const bool& enabled);
+    void set_exclude_rr_info(const bool& enabled);
+    /* Parse the string which contains the content to be excluded
+     * Accepted string format is [sb|cbx|cby]
+     * Allow the use ',' as splitter
+     * For example: sb,cby
+     */
+    void set_exclude_content(const std::string& content);
+    void set_include_gsb_names(const std::string& gsb_names);
+    void set_verbose_output(const bool& enabled);
+  public: /* Public validators */
+    /* Check if the following internal data is valid or not:
+     * - output directory is assigned
+     * - no parsing errors
+     */
+    bool valid() const;
+  private: /* Internal Data */
+    std::string output_directory_;
+    bool unique_module_only_;
+    /* Flags to mark what content to be skipped when outputting: 
+     * 0 : rr_info
+     * 1 : cbx
+     * 2 : cby
+     * 3 : sb
+     */
+    std::array<bool, 4> exclude_content_;
+
+    std::vector<std::string> include_gsb_names_;
+    bool verbose_output_;
+
+    /* A flag to indicate if the data parse is invalid or not */
+    int num_parse_errors_;
+};
+
+} /* End namespace openfpga*/
+
+#endif

openfpga/src/annotation/write_xml_device_rr_gsb.cpp

@@ -26,7 +26,8 @@ static
 void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp,
                                          const RRGraphView& rr_graph,
                                          const RRGSB& rr_gsb,
-                                         const enum e_side& gsb_side) {
+                                         const enum e_side& gsb_side,
+                                         const bool& include_rr_info) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -37,9 +38,11 @@ void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp,
     /* General information of this IPIN */
     fp << "\t<" << rr_node_typename[rr_graph.node_type(cur_rr_node)]
        << " side=\"" << gsb_side_manager.to_string() 
-       << "\" index=\"" << inode 
+       << "\" index=\"" << inode;
-       << "\" node_id=\"" << size_t(cur_rr_node)
+    if (include_rr_info) {
-       << "\" mux_size=\"" << get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node).size()
+       fp << "\" node_id=\"" << size_t(cur_rr_node);
+    }
+    fp << "\" mux_size=\"" << get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node).size()
        << "\">" 
        << std::endl; 
     /* General information of each driving nodes */
@@ -63,9 +66,11 @@ void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp,
       const RRSegmentId& des_segment_id = rr_gsb.get_chan_node_segment(chan_side, driver_node_index);
 
       fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_node)]
-         << "\" side=\"" << chan_side_manager.to_string() 
+         << "\" side=\"" << chan_side_manager.to_string(); 
-         << "\" node_id=\"" << size_t(driver_node)
+      if (include_rr_info) {
-         << "\" index=\"" << driver_node_index 
+         fp << "\" node_id=\"" << size_t(driver_node);
+      }
+      fp << "\" index=\"" << driver_node_index 
          << "\" segment_id=\"" << size_t(des_segment_id)
          << "\"/>" 
          << std::endl; 
@@ -85,7 +90,8 @@ void write_rr_gsb_chan_connection_to_xml(std::fstream& fp,
                                          const VprDeviceAnnotation& vpr_device_annotation,
                                          const RRGraphView& rr_graph,
                                          const RRGSB& rr_gsb,
-                                         const enum e_side& gsb_side) {
+                                         const enum e_side& gsb_side,
+                                         const bool& include_rr_info) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -113,13 +119,17 @@ void write_rr_gsb_chan_connection_to_xml(std::fstream& fp,
 
     fp << "\t<" << rr_node_typename[cur_node_type]
        << " side=\"" << gsb_side_manager.to_string() 
-       << "\" index=\"" << inode 
+       << "\" index=\"" << inode;
-       << "\" node_id=\"" << size_t(cur_rr_node)
+    if (include_rr_info) {
-       << "\" segment_id=\"" << size_t(src_segment_id)
+       fp << "\" node_id=\"" << size_t(cur_rr_node)
-       << "\" segment_name=\"" << rr_graph.rr_segments()[src_segment_id].name
+          << "\" segment_id=\"" << size_t(src_segment_id)
-       << "\" mux_size=\"" << driver_rr_edges.size()
+          << "\" segment_name=\"" << rr_graph.get_segment(src_segment_id).name;
-       << "\" sb_module_pin_name=\"" << generate_sb_module_track_port_name(cur_node_type, gsb_side, OUT_PORT) 
+    }
-       << "\">" 
+    fp << "\" mux_size=\"" << driver_rr_edges.size();
+    if (include_rr_info) {
+      fp << "\" sb_module_pin_name=\"" << generate_sb_module_track_port_name(cur_node_type, gsb_side, OUT_PORT);
+    }
+    fp << "\">" 
        << std::endl; 
 
     /* Direct connection: output the node on the opposite side */
@@ -127,12 +137,14 @@ void write_rr_gsb_chan_connection_to_xml(std::fstream& fp,
       SideManager oppo_side =  gsb_side_manager.get_opposite();
       fp << "\t\t<driver_node type=\"" << rr_node_typename[cur_node_type]
          << "\" side=\"" << oppo_side.to_string() 
-         << "\" index=\"" << rr_gsb.get_node_index(rr_graph, cur_rr_node, oppo_side.get_side(), IN_PORT)
+         << "\" index=\"" << rr_gsb.get_node_index(rr_graph, cur_rr_node, oppo_side.get_side(), IN_PORT);
-         << "\" node_id=\"" << size_t(cur_rr_node)
+      if (include_rr_info) {
-         << "\" segment_id=\"" << size_t(src_segment_id)
+        fp << "\" node_id=\"" << size_t(cur_rr_node)
-         << "\" segment_name=\"" << rr_graph.rr_segments()[src_segment_id].name
+           << "\" segment_id=\"" << size_t(src_segment_id)
-         << "\" sb_module_pin_name=\"" << generate_sb_module_track_port_name(cur_node_type, oppo_side.get_side(), IN_PORT) 
+           << "\" segment_name=\"" << rr_graph.get_segment(src_segment_id).name
-         << "\"/>" 
+           << "\" sb_module_pin_name=\"" << generate_sb_module_track_port_name(cur_node_type, oppo_side.get_side(), IN_PORT);
+      }
+      fp << "\"/>" 
          << std::endl; 
     } else {
       for (const RREdgeId& driver_rr_edge : driver_rr_edges) {
@@ -146,22 +158,26 @@ void write_rr_gsb_chan_connection_to_xml(std::fstream& fp,
         if (OPIN == rr_graph.node_type(driver_rr_node)) {
           fp << "\t\t<driver_node type=\"" << rr_node_typename[OPIN]
              << "\" side=\"" << driver_side.to_string() 
-             << "\" index=\"" << driver_node_index  
+             << "\" index=\"" << driver_node_index;
-             << "\" node_id=\"" << size_t(driver_rr_node)
+          if (include_rr_info) {
-             << "\" grid_side=\"" <<  rr_graph.node_side_string(driver_rr_node) 
+            fp << "\" node_id=\"" << size_t(driver_rr_node)
-             << "\" sb_module_pin_name=\"" << generate_sb_module_grid_port_name(gsb_side, driver_node_side, vpr_device_grid, vpr_device_annotation, rr_graph, driver_rr_node) 
+               << "\" grid_side=\"" << grid_side.to_string() 
-             <<"\"/>" 
+               << "\" sb_module_pin_name=\"" << generate_sb_module_grid_port_name(gsb_side, driver_node_side, vpr_device_grid, vpr_device_annotation, rr_graph, driver_rr_node); 
+          }
+          fp <<"\"/>" 
              << std::endl; 
         } else {
           const RRSegmentId& des_segment_id = rr_gsb.get_chan_node_segment(driver_node_side, driver_node_index);
           fp << "\t\t<driver_node type=\"" << rr_node_typename[rr_graph.node_type(driver_rr_node)]
              << "\" side=\"" << driver_side.to_string() 
-             << "\" index=\"" << driver_node_index 
+             << "\" index=\"" << driver_node_index; 
-             << "\" node_id=\"" << size_t(driver_rr_node)
+          if (include_rr_info) {
-             << "\" segment_id=\"" << size_t(des_segment_id)
+            fp << "\" node_id=\"" << size_t(driver_rr_node)
-             << "\" segment_name=\"" << rr_graph.rr_segments()[des_segment_id].name
+               << "\" segment_id=\"" << size_t(des_segment_id)
-             << "\" sb_module_pin_name=\"" << generate_sb_module_track_port_name(rr_graph.node_type(driver_rr_node), driver_side.get_side(), IN_PORT) 
+               << "\" segment_name=\"" << rr_graph.get_segment(des_segment_id).name
-             << "\"/>" 
+               << "\" sb_module_pin_name=\"" << generate_sb_module_track_port_name(rr_graph.node_type(driver_rr_node), driver_side.get_side(), IN_PORT); 
+          }
+          fp << "\"/>" 
              << std::endl; 
         }
       }  
@@ -181,14 +197,22 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
                                   const VprDeviceAnnotation& vpr_device_annotation,
                                   const RRGraphView& rr_graph,
                                   const RRGSB& rr_gsb,
-                                  const bool& verbose) {
+                                  const RRGSBWriterOption& options) {
+
   /* Prepare file name */
   std::string fname(fname_prefix);
-  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  vtr::Point<size_t> sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
-  fname += generate_switch_block_module_name(gsb_coordinate);
+  std::string curr_sb_name = generate_switch_block_module_name(sb_coordinate);
+  fname += curr_sb_name; 
   fname += ".xml";
 
-  VTR_LOGV(verbose,
+  /* If there is a list of gsb list, we skip those which are not in the list */
+  std::vector<std::string> include_gsb_names = options.include_gsb_names();
+  if (!include_gsb_names.empty() && include_gsb_names.end() == std::find(include_gsb_names.begin(), include_gsb_names.end(), curr_sb_name)) {
+    return;
+  }
+
+  VTR_LOGV(options.verbose_output(),
            "Output internal structure of Switch Block to '%s'\n",
            fname.c_str());
 
@@ -201,7 +225,7 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
   check_file_stream(fname.c_str(), fp);
 
   /* Output location of the Switch Block */
-  fp << "<rr_gsb x=\"" << rr_gsb.get_x() << "\" y=\"" << rr_gsb.get_y() << "\""
+  fp << "<rr_sb x=\"" << rr_gsb.get_x() << "\" y=\"" << rr_gsb.get_y() << "\""
      << " num_sides=\"" << rr_gsb.get_num_sides() << "\">" << std::endl;
 
   /* Output each side */ 
@@ -209,14 +233,62 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
     SideManager gsb_side_manager(side);
     enum e_side gsb_side = gsb_side_manager.get_side();
    
-    /* IPIN nodes and related connections */
-    write_rr_gsb_ipin_connection_to_xml(fp, rr_graph, rr_gsb, gsb_side);
-
     /* routing-track and related connections */
-    write_rr_gsb_chan_connection_to_xml(fp, vpr_device_grid, vpr_device_annotation, rr_graph, rr_gsb, gsb_side);
+    write_rr_gsb_chan_connection_to_xml(fp, vpr_device_grid, vpr_device_annotation, rr_graph, rr_gsb, gsb_side, options.include_rr_info());
   }
 
-  fp << "</rr_gsb>" 
+  fp << "</rr_sb>" 
+     << std::endl;
+
+  /* close a file */
+  fp.close();
+}
+
+/***************************************************************************************
+ * Output internal structure (only the connection block part) of a RRGSB to XML format 
+ ***************************************************************************************/
+static 
+void write_rr_connection_block_to_xml(const std::string fname_prefix,
+                                      const RRGraph& rr_graph,
+                                      const RRGSB& rr_gsb,
+                                      const t_rr_type& cb_type,
+                                      const RRGSBWriterOption& options) {
+  /* Prepare file name */
+  std::string fname(fname_prefix);
+  vtr::Point<size_t> cb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+  std::string curr_cb_name = generate_connection_block_module_name(cb_type, cb_coordinate);
+  fname += curr_cb_name; 
+  fname += ".xml";
+
+  /* If there is a list of gsb list, we skip those which are not in the list */
+  std::vector<std::string> include_gsb_names = options.include_gsb_names();
+  if (!include_gsb_names.empty() && include_gsb_names.end() == std::find(include_gsb_names.begin(), include_gsb_names.end(), curr_cb_name)) {
+    return;
+  }
+
+  VTR_LOGV(options.verbose_output(),
+           "Output internal structure of Connection Block to '%s'\n",
+           fname.c_str());
+
+  /* Create a file handler*/
+  std::fstream fp;
+  /* Open a file */
+  fp.open(fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(fname.c_str(), fp);
+
+  /* Output location of the Switch Block */
+  fp << "<rr_cb x=\"" << rr_gsb.get_cb_x(cb_type) << "\" y=\"" << rr_gsb.get_cb_y(cb_type) << "\""
+     << " num_sides=\"" << rr_gsb.get_num_sides() << "\">" << std::endl;
+
+  /* Output each side */ 
+  for (e_side side : rr_gsb.get_cb_ipin_sides(cb_type)) {
+    /* IPIN nodes and related connections */
+    write_rr_gsb_ipin_connection_to_xml(fp, rr_graph, rr_gsb, side, options.include_rr_info());
+  }
+
+  fp << "</rr_cb>" 
      << std::endl;
 
   /* close a file */
@@ -227,45 +299,74 @@ void write_rr_switch_block_to_xml(const std::string fname_prefix,
  * Output internal structure (only the switch block part) of all the RRGSBs
  * in a DeviceRRGSB  to XML format 
  ***************************************************************************************/
-void write_device_rr_gsb_to_xml(const char* sb_xml_dir, 
+void write_device_rr_gsb_to_xml(const DeviceGrid& vpr_device_grid,
-                                const DeviceGrid& vpr_device_grid,
                                 const VprDeviceAnnotation& vpr_device_annotation,
                                 const RRGraphView& rr_graph,
                                 const DeviceRRGSB& device_rr_gsb,
-                                const bool& unique,
+                                const RRGSBWriterOption& options) {
-                                const bool& verbose) {
+  std::string xml_dir_name = format_dir_path(options.output_directory());
-  std::string xml_dir_name = format_dir_path(std::string(sb_xml_dir));
 
   /* Create directories */
   create_directory(xml_dir_name);
 
   vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
 
-  size_t gsb_counter = 0;
+  size_t sb_counter = 0;
+  std::map<t_rr_type, size_t> cb_counters = { {CHANX, 0}, {CHANY, 0} };
+  std::map<t_rr_type, std::string> cb_names = { {CHANX, "X-direction"}, {CHANY, "Y-direction"} };
+
+  std::vector<std::string> include_gsb_names = options.include_gsb_names();
 
   /* For each switch block, an XML file will be outputted */
-  if (unique) {
+  if (options.unique_module_only()) {
     /* Only output unique GSB modules */
     VTR_LOG("Only output unique GSB modules to XML\n");
-    for (size_t igsb = 0; igsb < device_rr_gsb.get_num_gsb_unique_module(); ++igsb) {
+    for (size_t igsb = 0; igsb < device_rr_gsb.get_num_sb_unique_module(); ++igsb) {
-      const RRGSB& rr_gsb = device_rr_gsb.get_gsb_unique_module(igsb);
+      const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(igsb);
-      write_rr_switch_block_to_xml(xml_dir_name, vpr_device_grid, vpr_device_annotation, rr_graph, rr_gsb, verbose);
+      /* Write CBx, CBy, SB on need */
-      gsb_counter++;
+      if (options.include_sb_content()) {
+        write_rr_switch_block_to_xml(xml_dir_name, vpr_device_grid, vpr_device_annotation, rr_graph, rr_gsb, options);
+      }
+      sb_counter++;
+    }
+    for (t_rr_type cb_type : {CHANX, CHANY}) {
+      for (size_t igsb = 0; igsb < device_rr_gsb.get_num_cb_unique_module(cb_type); ++igsb) {
+        const RRGSB& rr_gsb = device_rr_gsb.get_cb_unique_module(cb_type, igsb);
+        if (options.include_cb_content(cb_type)) {
+          write_rr_connection_block_to_xml(xml_dir_name, rr_graph, rr_gsb, cb_type, options);
+          cb_counters[cb_type]++;
+        }
+      }
     } 
   } else {
     /* Output all GSB instances in the fabric (some instances may share the same module) */
     for (size_t ix = 0; ix < sb_range.x(); ++ix) {
       for (size_t iy = 0; iy < sb_range.y(); ++iy) {
         const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
-        write_rr_switch_block_to_xml(xml_dir_name, vpr_device_grid, vpr_device_annotation, rr_graph, rr_gsb, verbose);
+        /* Write CBx, CBy, SB on need */
-        gsb_counter++;
+        if (options.include_sb_content()) {
+          write_rr_switch_block_to_xml(xml_dir_name, vpr_device_grid, vpr_device_annotation, rr_graph, rr_gsb, options);
+          sb_counter++;
+        }
+        for (t_rr_type cb_type : {CHANX, CHANY}) {
+          if (options.include_cb_content(cb_type)) {
+            write_rr_connection_block_to_xml(xml_dir_name, rr_graph, rr_gsb, cb_type, options);
+            cb_counters[cb_type]++;
+          }
+        }
       }
     }
   }
 
-  VTR_LOG("Output %lu XML files to directory '%s'\n",
+  VTR_LOG("Output %lu Switch blocks to XML files under directory '%s'\n",
-          gsb_counter,
+          sb_counter,
           xml_dir_name.c_str());
+  for (t_rr_type cb_type : {CHANX, CHANY}) {
+    VTR_LOG("Output %lu %s Connection blocks to XML files under directory '%s'\n",
+            cb_counters[cb_type],
+            cb_names[cb_type].c_str(),
+            xml_dir_name.c_str());
+  }
 }
 
 } /* end namespace openfpga */

openfpga/src/annotation/write_xml_device_rr_gsb.h

@@ -9,6 +9,7 @@
 #include "vpr_device_annotation.h"
 #include "rr_graph_view.h"
 #include "device_rr_gsb.h"
+#include "rr_gsb_writer_option.h"
 
 /********************************************************************
  * Function declaration
@@ -17,13 +18,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void write_device_rr_gsb_to_xml(const char* sb_xml_dir,
+void write_device_rr_gsb_to_xml(const DeviceGrid& vpr_device_grid,
-                                const DeviceGrid& vpr_device_grid,
                                 const VprDeviceAnnotation& vpr_device_annotation,
                                 const RRGraphView& rr_graph,
                                 const DeviceRRGSB& device_rr_gsb,
-                                const bool& unique,
+                                const RRGSBWriterOption& options);
-                                const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/base/openfpga_setup_command.cpp

@@ -213,6 +213,17 @@ ShellCommandId add_openfpga_write_gsb_command(openfpga::Shell<OpenfpgaContext>&
   /* Add an option '--unique' */
   shell_cmd.add_option("unique", false, "Only output unique GSB blocks");
 
+  /* Add an option '--exclude_rr_info' */
+  shell_cmd.add_option("exclude_rr_info", false, "Exclude routing resource graph information from output files, e.g., node id as well as other attributes. This is useful to check the connection inside GSBs purely.");
+
+  /* Add an option '--exclude'*/
+  CommandOptionId opt_exclude = shell_cmd.add_option("exclude", false, "Exclude part of the GSB data to be outputted. Can be [``sb``|``cbx``|``cby``]. Users can exclude multiple parts by using a splitter ``,``");
+  shell_cmd.set_option_require_value(opt_exclude, openfpga::OPT_STRING);
+
+  /* Add an option '--gsb_names'*/
+  CommandOptionId opt_gsb_names = shell_cmd.add_option("gsb_names", false, "Specify the name of GSB to be outputted. Users can specify multiple GSBs by using a splitter ``,``");
+  shell_cmd.set_option_require_value(opt_gsb_names, openfpga::OPT_STRING);
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Show verbose outputs");
 

openfpga/src/base/openfpga_write_gsb.cpp

@@ -34,17 +34,30 @@ int write_gsb(const OpenfpgaContext& openfpga_ctx,
   VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
 
   CommandOptionId opt_unique = cmd.option("unique");
+  CommandOptionId opt_exclude_rr_info = cmd.option("exclude_rr_info");
+  CommandOptionId opt_exclude = cmd.option("exclude");
+  CommandOptionId opt_gsb_names = cmd.option("gsb_names");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
-  std::string sb_file_name = cmd_context.option_value(cmd, opt_file);
+  /* Build the options for the writer */
+  RRGSBWriterOption options;
+  options.set_output_directory(cmd_context.option_value(cmd, opt_file));
+  options.set_unique_module_only(cmd_context.option_enable(cmd, opt_unique));
+  options.set_exclude_rr_info(cmd_context.option_enable(cmd, opt_exclude_rr_info));
+  options.set_exclude_content(cmd_context.option_value(cmd, opt_exclude));
+  options.set_include_gsb_names(cmd_context.option_value(cmd, opt_gsb_names));
+  options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
 
-  write_device_rr_gsb_to_xml(sb_file_name.c_str(),
+  if (!options.valid()) {
-                             g_vpr_ctx.device().grid,
+    VTR_LOG("Detected errors when parsing options!\n");
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  write_device_rr_gsb_to_xml(g_vpr_ctx.device().grid,
                              openfpga_ctx.vpr_device_annotation(),
                              g_vpr_ctx.device().rr_graph,
                              openfpga_ctx.device_rr_gsb(),
-                             cmd_context.option_enable(cmd, opt_unique),
+                             options);
-                             cmd_context.option_enable(cmd, opt_verbose));
 
   /* TODO: should identify the error code from internal function execution */
   return CMD_EXEC_SUCCESS;

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -155,6 +155,17 @@ clear-task-run basic_tests/explicit_multi_verilog_files $@
 
 echo -e "Testing write GSB to files";
 run-task basic_tests/write_gsb/write_gsb_to_xml $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_rr_info $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cby $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx_cby $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cbx $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cby $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_include_sb_cbx_cby $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cbx $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cby $@
+run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_sb $@
 run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@
 run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@
 run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--exclude cbx
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx_cby/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--exclude cbx,cby
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_exclude_cby/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--exclude cby
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_exclude_rr_info/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--exclude_rr_info
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_exclude_sb/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--exclude sb
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cbx/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--exclude sb,cbx
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cby/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--exclude sb,cby
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_include_sb_cbx_cby/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--gsb_names sb_1__1_,cbx_1__0_,cby_1__1_
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_include_single_cbx/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--gsb_names sb_1__1_
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_include_single_cby/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=--gsb_names cby_0__1_
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/basic_tests/write_gsb/write_gsb_to_xml_include_single_sb/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+openfpga_build_fabric_option=
+openfpga_write_gsb_option=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

yosys-plugins

@@ -1 +1 @@
-Subproject commit da931732ce06f4d42f6505f69763987659f2db31
+Subproject commit 0713ed79abaa99afc5f9a102f53c7a6256144927