bring bitstream generator for routing modules online
This commit is contained in:
tangxifan
parent
86c7c24701
commit
712eeb1340
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@ -14,7 +14,7 @@
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#include "openfpga_naming.h"
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#include "openfpga_naming.h"
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//#include "build_grid_bitstream.h"
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//#include "build_grid_bitstream.h"
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//#include "build_routing_bitstream.h"
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#include "build_routing_bitstream.h"
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#include "build_device_bitstream.h"
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#include "build_device_bitstream.h"
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/* begin namespace openfpga */
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/* begin namespace openfpga */
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@ -60,9 +60,18 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
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/* Create bitstream from routing architectures */
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/* Create bitstream from routing architectures */
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VTR_LOGV(verbose, "Building routing bitstream...\n");
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VTR_LOGV(verbose, "Building routing bitstream...\n");
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//build_routing_bitstream(bitstream_manager, top_block, module_manager, circuit_lib, mux_lib, rr_switches, L_rr_node, L_device_rr_gsb);
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build_routing_bitstream(bitstream_manager, top_block,
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openfpga_ctx.module_graph(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.mux_lib(),
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.vpr_routing_annotation(),
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vpr_ctx.device().rr_graph,
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openfpga_ctx.device_rr_gsb());
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VTR_LOGV(verbose, "Done\n");
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VTR_LOGV(verbose, "Done\n");
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VTR_LOGV(verbose, "Decoded %lu configuration bits\n", bitstream_manager.bits().size());
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return bitstream_manager;
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return bitstream_manager;
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}
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}
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@ -13,17 +13,12 @@
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#include "mux_utils.h"
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#include "mux_utils.h"
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#include "decoder_library_utils.h"
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#include "decoder_library_utils.h"
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#include "mux_bitstream_constants.h"
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#include "build_mux_bitstream.h"
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#include "build_mux_bitstream.h"
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/* begin namespace openfpga */
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/* begin namespace openfpga */
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namespace openfpga {
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namespace openfpga {
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/* Default path ID of a unused multiplexer */
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#define DEFAULT_PATH_ID -1
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/* Default path ID of a unused multiplexer when there are no constant inputs*/
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#define DEFAULT_MUX_PATH_ID 0
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/********************************************************************
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/********************************************************************
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* Find the default path id of a MUX
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* Find the default path id of a MUX
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* This is applied when the path id specified is DEFAULT_PATH_ID,
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* This is applied when the path id specified is DEFAULT_PATH_ID,
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@ -0,0 +1,442 @@
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/********************************************************************
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* This file includes functions to build bitstream from global routing
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* architecture of a mapped FPGA fabric
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* We decode the bitstream from configuration of routing multiplexers
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* which locate in global routing architecture
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*******************************************************************/
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#include <vector>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_side_manager.h"
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#include "mux_utils.h"
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#include "rr_gsb_utils.h"
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#include "openfpga_reserved_words.h"
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#include "openfpga_naming.h"
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#include "openfpga_rr_graph_utils.h"
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#include "mux_bitstream_constants.h"
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#include "build_mux_bitstream.h"
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#include "build_routing_bitstream.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function generates bitstream for a routing multiplexer
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* This function will identify if a node indicates a routing multiplexer
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* If not a routing multiplexer, no bitstream is needed here
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* If yes, we will generate the bitstream for the routing multiplexer
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*******************************************************************/
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static
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void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& mux_mem_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const RRGraph& rr_graph,
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const RRNodeId& cur_rr_node,
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const std::vector<RRNodeId>& drive_rr_nodes,
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const VprDeviceAnnotation& device_annotation,
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const VprRoutingAnnotation& routing_annotation) {
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/* Check current rr_node is CHANX or CHANY*/
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VTR_ASSERT( (CHANX == rr_graph.node_type(cur_rr_node))
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|| (CHANY == rr_graph.node_type(cur_rr_node)));
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/* Find the input size of the implementation of a routing multiplexer */
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size_t datapath_mux_size = drive_rr_nodes.size();
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/* Find out which routing path is used in this MUX */
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int path_id = DEFAULT_PATH_ID;
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for (size_t inode = 0; inode < drive_rr_nodes.size(); ++inode) {
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if (routing_annotation.rr_node_net(drive_rr_nodes[inode]) == routing_annotation.rr_node_net(cur_rr_node)) {
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path_id = (int)inode;
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break;
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}
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}
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/* Ensure that our path id makes sense! */
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VTR_ASSERT( (DEFAULT_PATH_ID == path_id)
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|| ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) )
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);
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/* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */
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std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, cur_rr_node);
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VTR_ASSERT(1 == driver_switches.size());
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CircuitModelId mux_model = device_annotation.rr_switch_circuit_model(driver_switches[0]);
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/* Generate bitstream depend on both technology and structure of this MUX */
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std::vector<bool> mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id);
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/* Find the module in module manager and ensure the bitstream size matches! */
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std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX));
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ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
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VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
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ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
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VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
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/* Add the bistream to the bitstream manager */
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for (const bool& bit : mux_bitstream) {
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ConfigBitId config_bit = bitstream_manager.add_bit(bit);
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/* Link the memory bits to the mux mem block */
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bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
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}
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}
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/********************************************************************
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* This function generates bitstream for an interconnection,
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* i.e., a routing multiplexer, in a Switch Block
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* This function will identify if a node indicates a routing multiplexer
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* If not a routing multiplexer, no bitstream is needed here
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* If yes, we will generate the bitstream for the routing multiplexer
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*******************************************************************/
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static
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void build_switch_block_interc_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& sb_configurable_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const RRGraph& rr_graph,
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const VprDeviceAnnotation& device_annotation,
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const VprRoutingAnnotation& routing_annotation,
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const RRGSB& rr_gsb,
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const e_side& chan_side,
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const size_t& chan_node_id) {
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std::vector<RRNodeId> driver_rr_nodes;
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/* Get the node */
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const RRNodeId& cur_rr_node = rr_gsb.get_chan_node(chan_side, chan_node_id);
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/* Determine if the interc lies inside a channel wire, that is interc between segments */
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if (false == rr_gsb.is_sb_node_passing_wire(rr_graph, chan_side, chan_node_id)) {
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driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, cur_rr_node);
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/* Special: if there are zero-driver nodes. We skip here */
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if (0 == driver_rr_nodes.size()) {
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return;
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}
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}
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if ( (0 == driver_rr_nodes.size())
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|| (0 == driver_rr_nodes.size()) ) {
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/* No bitstream generation required by a special direct connection*/
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return;
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} else if (1 < driver_rr_nodes.size()) {
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/* Create the block denoting the memory instances that drives this node in Switch Block */
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std::string mem_block_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MEM_INSTANCE_PREFIX, chan_side, chan_node_id, std::string(""));
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ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
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bitstream_manager.add_child_block(sb_configurable_block, mux_mem_block);
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/* This is a routing multiplexer! Generate bitstream */
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build_switch_block_mux_bitstream(bitstream_manager, mux_mem_block, module_manager,
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circuit_lib, mux_lib, rr_graph,
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cur_rr_node, driver_rr_nodes,
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device_annotation, routing_annotation);
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} /*Nothing should be done else*/
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}
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/********************************************************************
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* This function generates bitstream for a Switch Block
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* and add it to the bitstream manager
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* This function will spot all the routing multiplexers in a Switch Block
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* using a simple but effective rule:
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* The fan-in of each output node.
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* If there are more than 2 fan-in, there is a routing multiplexer
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*
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* Note that the output nodes typically spread over all the sides of a Switch Block
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* So, we will iterate over that.
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*******************************************************************/
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static
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void build_switch_block_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& sb_config_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const VprDeviceAnnotation& device_annotation,
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const VprRoutingAnnotation& routing_annotation,
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const RRGraph& rr_graph,
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const RRGSB& rr_gsb) {
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/* Iterate over all the multiplexers */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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SideManager side_manager(side);
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for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
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VTR_ASSERT( (CHANX == rr_graph.node_type(rr_gsb.get_chan_node(side_manager.get_side(), itrack)))
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|| (CHANY == rr_graph.node_type(rr_gsb.get_chan_node(side_manager.get_side(), itrack))) );
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/* Only output port indicates a routing multiplexer */
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if (OUT_PORT != rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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continue;
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}
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build_switch_block_interc_bitstream(bitstream_manager, sb_config_block,
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module_manager,
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circuit_lib, mux_lib, rr_graph,
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device_annotation, routing_annotation,
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rr_gsb, side_manager.get_side(), itrack);
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}
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}
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}
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/********************************************************************
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* This function generates bitstream for a routing multiplexer
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* in a Connection block
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* This function will identify if a node indicates a routing multiplexer
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* If not a routing multiplexer, no bitstream is needed here
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* If yes, we will generate the bitstream for the routing multiplexer
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*******************************************************************/
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static
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void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& mux_mem_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const VprDeviceAnnotation& device_annotation,
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const VprRoutingAnnotation& routing_annotation,
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const RRGraph& rr_graph,
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const RRNodeId& src_rr_node) {
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/* Find drive_rr_nodes*/
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size_t datapath_mux_size = rr_graph.node_fan_in(src_rr_node);
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/* Configuration bits for MUX*/
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int path_id = DEFAULT_PATH_ID;
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int edge_index = 0;
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for (const RREdgeId& edge : rr_graph.node_in_edges(src_rr_node)) {
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RRNodeId driver_node = rr_graph.edge_src_node(edge);
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if (routing_annotation.rr_node_net(driver_node) == routing_annotation.rr_node_net(src_rr_node)) {
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path_id = edge_index;
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break;
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}
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edge_index++;
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}
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/* Ensure that our path id makes sense! */
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VTR_ASSERT( (DEFAULT_PATH_ID == path_id)
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|| ( (DEFAULT_PATH_ID < path_id) && (path_id < (int)datapath_mux_size) )
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);
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/* Find the circuit model id of the mux, we need its design technology which matters the bitstream generation */
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std::vector<RRSwitchId> driver_switches = get_rr_graph_driver_switches(rr_graph, src_rr_node);
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VTR_ASSERT(1 == driver_switches.size());
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CircuitModelId mux_model = device_annotation.rr_switch_circuit_model(driver_switches[0]);
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/* Generate bitstream depend on both technology and structure of this MUX */
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std::vector<bool> mux_bitstream = build_mux_bitstream(circuit_lib, mux_model, mux_lib, datapath_mux_size, path_id);
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/* Find the module in module manager and ensure the bitstream size matches! */
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std::string mem_module_name = generate_mux_subckt_name(circuit_lib, mux_model, datapath_mux_size, std::string(MEMORY_MODULE_POSTFIX));
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ModuleId mux_mem_module = module_manager.find_module(mem_module_name);
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VTR_ASSERT (true == module_manager.valid_module_id(mux_mem_module));
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ModulePortId mux_mem_out_port_id = module_manager.find_module_port(mux_mem_module, generate_configuration_chain_data_out_name());
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VTR_ASSERT(mux_bitstream.size() == module_manager.module_port(mux_mem_module, mux_mem_out_port_id).get_width());
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/* Add the bistream to the bitstream manager */
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for (const bool& bit : mux_bitstream) {
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ConfigBitId config_bit = bitstream_manager.add_bit(bit);
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/* Link the memory bits to the mux mem block */
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bitstream_manager.add_bit_to_block(mux_mem_block, config_bit);
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}
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}
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/********************************************************************
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* This function generates bitstream for an interconnection,
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* i.e., a routing multiplexer, in a Connection Block
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* This function will identify if a node indicates a routing multiplexer
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* If not a routing multiplexer, no bitstream is needed here
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* If yes, we will generate the bitstream for the routing multiplexer
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*******************************************************************/
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static
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void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager,
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const ConfigBlockId& cb_configurable_block,
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const ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const VprDeviceAnnotation& device_annotation,
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const VprRoutingAnnotation& routing_annotation,
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const RRGraph& rr_graph,
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const RRGSB& rr_gsb,
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const e_side& cb_ipin_side,
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const size_t& ipin_index) {
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RRNodeId src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
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/* Consider configurable edges only */
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std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, src_rr_node);
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if (1 == driver_rr_nodes.size()) {
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/* No bitstream generation required by a special direct connection*/
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} else if (1 < driver_rr_nodes.size()) {
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/* Create the block denoting the memory instances that drives this node in Switch Block */
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||||||
|
std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_graph.node_side(src_rr_node), ipin_index, std::string(""));
|
||||||
|
ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
|
||||||
|
bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block);
|
||||||
|
/* This is a routing multiplexer! Generate bitstream */
|
||||||
|
build_connection_block_mux_bitstream(bitstream_manager, mux_mem_block,
|
||||||
|
module_manager, circuit_lib, mux_lib,
|
||||||
|
device_annotation, routing_annotation,
|
||||||
|
rr_graph, src_rr_node);
|
||||||
|
} /*Nothing should be done else*/
|
||||||
|
}
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* This function generates bitstream for a Connection Block
|
||||||
|
* and add it to the bitstream manager
|
||||||
|
* This function will spot all the routing multiplexers in a Connection Block
|
||||||
|
* using a simple but effective rule:
|
||||||
|
* The fan-in of each output node.
|
||||||
|
* If there are more than 2 fan-in, there is a routing multiplexer
|
||||||
|
*
|
||||||
|
* Note that the output nodes are the IPIN rr node in a Connection Block
|
||||||
|
* So, we will iterate over that.
|
||||||
|
*******************************************************************/
|
||||||
|
static
|
||||||
|
void build_connection_block_bitstream(BitstreamManager& bitstream_manager,
|
||||||
|
const ConfigBlockId& cb_configurable_block,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const MuxLibrary& mux_lib,
|
||||||
|
const VprDeviceAnnotation& device_annotation,
|
||||||
|
const VprRoutingAnnotation& routing_annotation,
|
||||||
|
const RRGraph& rr_graph,
|
||||||
|
const RRGSB& rr_gsb,
|
||||||
|
const t_rr_type& cb_type) {
|
||||||
|
|
||||||
|
/* Find routing multiplexers on the sides of a Connection block where IPIN nodes locate */
|
||||||
|
std::vector<enum e_side> cb_sides = rr_gsb.get_cb_ipin_sides(cb_type);
|
||||||
|
|
||||||
|
for (size_t side = 0; side < cb_sides.size(); ++side) {
|
||||||
|
enum e_side cb_ipin_side = cb_sides[side];
|
||||||
|
SideManager side_manager(cb_ipin_side);
|
||||||
|
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
|
||||||
|
build_connection_block_interc_bitstream(bitstream_manager, cb_configurable_block,
|
||||||
|
module_manager, circuit_lib, mux_lib,
|
||||||
|
device_annotation, routing_annotation,
|
||||||
|
rr_graph, rr_gsb,
|
||||||
|
cb_ipin_side, inode);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Create bitstream for a X-direction or Y-direction Connection Blocks
|
||||||
|
*******************************************************************/
|
||||||
|
static
|
||||||
|
void build_connection_block_bitstreams(BitstreamManager& bitstream_manager,
|
||||||
|
const ConfigBlockId& top_configurable_block,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const MuxLibrary& mux_lib,
|
||||||
|
const VprDeviceAnnotation& device_annotation,
|
||||||
|
const VprRoutingAnnotation& routing_annotation,
|
||||||
|
const RRGraph& rr_graph,
|
||||||
|
const DeviceRRGSB& device_rr_gsb,
|
||||||
|
const t_rr_type& cb_type) {
|
||||||
|
|
||||||
|
vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
|
||||||
|
|
||||||
|
for (size_t ix = 0; ix < cb_range.x(); ++ix) {
|
||||||
|
for (size_t iy = 0; iy < cb_range.y(); ++iy) {
|
||||||
|
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
|
||||||
|
/* Check if the connection block exists in the device!
|
||||||
|
* Some of them do NOT exist due to heterogeneous blocks (height > 1)
|
||||||
|
* We will skip those modules
|
||||||
|
*/
|
||||||
|
if (false == rr_gsb.is_cb_exist(cb_type)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
/* Skip if the cb does not contain any configuration bits! */
|
||||||
|
if (true == connection_block_contain_only_routing_tracks(rr_gsb, cb_type)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
/* Create a block for the bitstream which corresponds to the Switch block */
|
||||||
|
vtr::Point<size_t> cb_coord(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
|
||||||
|
ConfigBlockId cb_configurable_block = bitstream_manager.add_block(generate_connection_block_module_name(cb_type, cb_coord));
|
||||||
|
/* Set switch block as a child of top block */
|
||||||
|
bitstream_manager.add_child_block(top_configurable_block, cb_configurable_block);
|
||||||
|
|
||||||
|
build_connection_block_bitstream(bitstream_manager, cb_configurable_block, module_manager,
|
||||||
|
circuit_lib, mux_lib,
|
||||||
|
device_annotation, routing_annotation,
|
||||||
|
rr_graph,
|
||||||
|
rr_gsb, cb_type);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Top-level function to create bitstream for global routing architecture
|
||||||
|
* Two major tasks:
|
||||||
|
* 1. Generate bitstreams for Switch Blocks
|
||||||
|
* 2. Generate bitstreams for both X-direction and Y-direction Connection Blocks
|
||||||
|
*******************************************************************/
|
||||||
|
void build_routing_bitstream(BitstreamManager& bitstream_manager,
|
||||||
|
const ConfigBlockId& top_configurable_block,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const MuxLibrary& mux_lib,
|
||||||
|
const VprDeviceAnnotation& device_annotation,
|
||||||
|
const VprRoutingAnnotation& routing_annotation,
|
||||||
|
const RRGraph& rr_graph,
|
||||||
|
const DeviceRRGSB& device_rr_gsb) {
|
||||||
|
|
||||||
|
/* Generate bitstream for each switch blocks
|
||||||
|
* To organize the bitstream in blocks, we create a block for each switch block
|
||||||
|
* and give names which are same as they are in top-level module managers
|
||||||
|
*/
|
||||||
|
VTR_LOG("Generating bitstream for Switch blocks...");
|
||||||
|
vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
|
||||||
|
for (size_t ix = 0; ix < sb_range.x(); ++ix) {
|
||||||
|
for (size_t iy = 0; iy < sb_range.y(); ++iy) {
|
||||||
|
const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
|
||||||
|
/* Check if the switch block exists in the device!
|
||||||
|
* Some of them do NOT exist due to heterogeneous blocks (width > 1)
|
||||||
|
* We will skip those modules
|
||||||
|
*/
|
||||||
|
if (false == rr_gsb.is_sb_exist()) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Create a block for the bitstream which corresponds to the Switch block */
|
||||||
|
vtr::Point<size_t> sb_coord(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
|
||||||
|
ConfigBlockId sb_configurable_block = bitstream_manager.add_block(generate_switch_block_module_name(sb_coord));
|
||||||
|
/* Set switch block as a child of top block */
|
||||||
|
bitstream_manager.add_child_block(top_configurable_block, sb_configurable_block);
|
||||||
|
|
||||||
|
build_switch_block_bitstream(bitstream_manager, sb_configurable_block, module_manager,
|
||||||
|
circuit_lib, mux_lib,
|
||||||
|
device_annotation, routing_annotation,
|
||||||
|
rr_graph,
|
||||||
|
rr_gsb);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
VTR_LOG("Done\n");
|
||||||
|
|
||||||
|
/* Generate bitstream for each connection blocks
|
||||||
|
* To organize the bitstream in blocks, we create a block for each connection block
|
||||||
|
* and give names which are same as they are in top-level module managers
|
||||||
|
*/
|
||||||
|
VTR_LOG("Generating bitstream for X-direction Connection blocks ...");
|
||||||
|
|
||||||
|
build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager,
|
||||||
|
circuit_lib, mux_lib,
|
||||||
|
device_annotation, routing_annotation,
|
||||||
|
rr_graph,
|
||||||
|
device_rr_gsb, CHANX);
|
||||||
|
VTR_LOG("Done\n");
|
||||||
|
|
||||||
|
VTR_LOG("Generating bitstream for Y-direction Connection blocks ...");
|
||||||
|
|
||||||
|
build_connection_block_bitstreams(bitstream_manager, top_configurable_block, module_manager,
|
||||||
|
circuit_lib, mux_lib,
|
||||||
|
device_annotation, routing_annotation,
|
||||||
|
rr_graph,
|
||||||
|
device_rr_gsb, CHANY);
|
||||||
|
VTR_LOG("Done");
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
} /* end namespace openfpga */
|
||||||
|
|
@ -0,0 +1,39 @@
|
||||||
|
/********************************************************************
|
||||||
|
* Header file for build_routing_bitstream.cpp
|
||||||
|
*******************************************************************/
|
||||||
|
#ifndef BUILD_ROUTING_BITSTREAM_H
|
||||||
|
#define BUILD_ROUTING_BITSTREAM_H
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Include header files that are required by function declaration
|
||||||
|
*******************************************************************/
|
||||||
|
#include <vector>
|
||||||
|
#include "bitstream_manager.h"
|
||||||
|
#include "vpr_context.h"
|
||||||
|
#include "module_manager.h"
|
||||||
|
#include "circuit_library.h"
|
||||||
|
#include "mux_library.h"
|
||||||
|
#include "device_rr_gsb.h"
|
||||||
|
#include "vpr_device_annotation.h"
|
||||||
|
#include "vpr_routing_annotation.h"
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Function declaration
|
||||||
|
*******************************************************************/
|
||||||
|
|
||||||
|
/* begin namespace openfpga */
|
||||||
|
namespace openfpga {
|
||||||
|
|
||||||
|
void build_routing_bitstream(BitstreamManager& bitstream_manager,
|
||||||
|
const ConfigBlockId& top_configurable_block,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const CircuitLibrary& circuit_lib,
|
||||||
|
const MuxLibrary& mux_lib,
|
||||||
|
const VprDeviceAnnotation& device_annotation,
|
||||||
|
const VprRoutingAnnotation& routing_annotation,
|
||||||
|
const RRGraph& rr_graph,
|
||||||
|
const DeviceRRGSB& device_rr_gsb);
|
||||||
|
|
||||||
|
} /* end namespace openfpga */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,15 @@
|
||||||
|
#ifndef MUX_BITSTREAM_CONSTANTS_H
|
||||||
|
#define MUX_BITSTREAM_CONSTANTS_H
|
||||||
|
|
||||||
|
/* begin namespace openfpga */
|
||||||
|
namespace openfpga {
|
||||||
|
|
||||||
|
/* Default path ID of a unused multiplexer */
|
||||||
|
#define DEFAULT_PATH_ID -1
|
||||||
|
|
||||||
|
/* Default path ID of a unused multiplexer when there are no constant inputs*/
|
||||||
|
#define DEFAULT_MUX_PATH_ID 0
|
||||||
|
|
||||||
|
} /* end namespace openfpga */
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue