From 7119075253585d5fe8c66b954e87192792f7aaf1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 29 Jun 2021 15:52:42 -0600 Subject: [PATCH] [Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated --- openfpga_flow/scripts/run_fpga_flow.py | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 1593d3f85..a333ebb8f 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -741,11 +741,6 @@ def run_netlists_verification(exit_if_fail=True): command = [cad_tools["iverilog_path"]] command += ["-o", compiled_file] - fpga_define_file = "./SRC/define_simulation.v" - fpga_define_file_bk = "./SRC/define_simulation.v.bak" - shutil.copy(fpga_define_file, fpga_define_file_bk) - with open(fpga_define_file, "r") as fp: - fpga_defines = fp.readlines() command += ["./SRC/%s_include_netlists.v" % args.top_module] command += ["-s"] @@ -753,11 +748,6 @@ def run_netlists_verification(exit_if_fail=True): command += [tb_top_formal] else: command += [tb_top_autochecked] - with open(fpga_define_file, "w") as fp: - for eachLine in fpga_defines: - if not (("ENABLE_FORMAL_VERIFICATION" in eachLine) or - "FORMAL_SIMULATION" in eachLine): - fp.write(eachLine) run_command("iverilog_verification", "iverilog_output.txt", command) vvp_command = ["vvp", compiled_file]