riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] fixing bugs in the preconfig module when supporting dut module of fpga_core

This commit is contained in:
tangxifan 2023-06-26 10:03:19 -07:00
parent 919d6d8608
commit 70f40cd21a
3 changed files with 26 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
libs/libfpgabitstream/src/bitstream_manager_utils.cpp
View File

@ -19,15 +19,20 @@ namespace openfpga {
* Return a vector of the block ids, where the top-level block * Return a vector of the block ids, where the top-level block
* locates in the head, while the leaf block locates in the tail * locates in the head, while the leaf block locates in the tail
* top, next, ... , block * top, next, ... , block
* Optionally, the top block name in the path can be specified. Useful to trim the hierarchy with a given range
*******************************************************************/ *******************************************************************/
std::vector<ConfigBlockId> find_bitstream_manager_block_hierarchy( std::vector<ConfigBlockId> find_bitstream_manager_block_hierarchy(
const BitstreamManager& bitstream_manager, const ConfigBlockId& block) { const BitstreamManager& bitstream_manager, const ConfigBlockId& block, const std::string& top_block_name) {
std::vector<ConfigBlockId> block_hierarchy; std::vector<ConfigBlockId> block_hierarchy;
ConfigBlockId temp_block = block; ConfigBlockId temp_block = block;
/* Generate a tree of parent block */ /* Generate a tree of parent block */
while (true == bitstream_manager.valid_block_id(temp_block)) { while (true == bitstream_manager.valid_block_id(temp_block)) {
block_hierarchy.push_back(temp_block); block_hierarchy.push_back(temp_block);
/* Check if we have reached the designated top block */
if (!top_block_name.empty() && bitstream_manager.block_name(temp_block) == top_block_name) {
break;
}
/* Go to upper level */ /* Go to upper level */
temp_block = bitstream_manager.block_parent(temp_block); temp_block = bitstream_manager.block_parent(temp_block);
} }

2
libs/libfpgabitstream/src/bitstream_manager_utils.h
View File

@ -16,7 +16,7 @@
namespace openfpga { namespace openfpga {
std::vector<ConfigBlockId> find_bitstream_manager_block_hierarchy( std::vector<ConfigBlockId> find_bitstream_manager_block_hierarchy(
const BitstreamManager& bitstream_manager, const ConfigBlockId& block); const BitstreamManager& bitstream_manager, const ConfigBlockId& block, const std::string& top_block_name = "");
std::vector<ConfigBlockId> find_bitstream_manager_top_blocks( std::vector<ConfigBlockId> find_bitstream_manager_top_blocks(
const BitstreamManager& bitstream_manager); const BitstreamManager& bitstream_manager);

49
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -306,8 +306,7 @@ static int print_verilog_preconfig_top_module_connect_global_ports(
* while uses 'force' syntax to impost the bitstream at mem_inv port * while uses 'force' syntax to impost the bitstream at mem_inv port
*******************************************************************/ *******************************************************************/
static void print_verilog_preconfig_top_module_force_bitstream( static void print_verilog_preconfig_top_module_force_bitstream(
std::fstream &fp, const ModuleManager &module_manager, std::fstream &fp, const std::string& top_block_name, const BitstreamManager &bitstream_manager,
const ModuleId &top_module, const BitstreamManager &bitstream_manager,
const bool &output_datab_bits) { const bool &output_datab_bits) {
/* Validate the file stream */ /* Validate the file stream */
valid_file_stream(fp); valid_file_stream(fp);
@ -326,19 +325,10 @@ static void print_verilog_preconfig_top_module_force_bitstream(
/* Build the hierarchical path of the configuration bit in modules */ /* Build the hierarchical path of the configuration bit in modules */
std::vector<ConfigBlockId> block_hierarchy = std::vector<ConfigBlockId> block_hierarchy =
find_bitstream_manager_block_hierarchy(bitstream_manager, find_bitstream_manager_block_hierarchy(bitstream_manager,
config_block_id); config_block_id, top_block_name);
/* Drop the first block, which is the top module, it should be replaced by
* the instance name here */
/* Ensure that this is the module we want to drop! */ /* Ensure that this is the module we want to drop! */
VTR_LOG("Top module: '%s', Block[0]: '%s', Block[1]: '%s'\n", module_manager.module_name(top_module).c_str(), bitstream_manager.block_name(block_hierarchy[0]).c_str(), bitstream_manager.block_name(block_hierarchy[1]).c_str()); VTR_ASSERT(top_block_name == bitstream_manager.block_name(block_hierarchy[0]));
VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])) block_hierarchy.erase(block_hierarchy.begin());
|| 0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1])));
if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))) {
block_hierarchy.erase(block_hierarchy.begin());
} else if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1]))) {
block_hierarchy.erase(block_hierarchy.begin());
block_hierarchy.erase(block_hierarchy.begin());
}
/* Build the full hierarchy path */ /* Build the full hierarchy path */
std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME); std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
for (const ConfigBlockId &temp_block : block_hierarchy) { for (const ConfigBlockId &temp_block : block_hierarchy) {
@ -391,8 +381,7 @@ static void print_verilog_preconfig_top_module_force_bitstream(
* This function uses '$deposit' syntax to do so * This function uses '$deposit' syntax to do so
*******************************************************************/ *******************************************************************/
static void print_verilog_preconfig_top_module_deposit_bitstream( static void print_verilog_preconfig_top_module_deposit_bitstream(
std::fstream &fp, const ModuleManager &module_manager, std::fstream &fp, const std::string& top_block_name, const BitstreamManager &bitstream_manager,
const ModuleId &top_module, const BitstreamManager &bitstream_manager,
const bool &output_datab_bits) { const bool &output_datab_bits) {
/* Validate the file stream */ /* Validate the file stream */
valid_file_stream(fp); valid_file_stream(fp);
@ -411,18 +400,12 @@ static void print_verilog_preconfig_top_module_deposit_bitstream(
/* Build the hierarchical path of the configuration bit in modules */ /* Build the hierarchical path of the configuration bit in modules */
std::vector<ConfigBlockId> block_hierarchy = std::vector<ConfigBlockId> block_hierarchy =
find_bitstream_manager_block_hierarchy(bitstream_manager, find_bitstream_manager_block_hierarchy(bitstream_manager,
config_block_id); config_block_id, top_block_name);
/* Drop the first block, which is the top module, it should be replaced by /* Drop the first block, which is the top module, it should be replaced by
* the instance name here */ * the instance name here */
/* Ensure that this is the module we want to drop! */ /* Ensure that this is the module we want to drop! */
VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0])) VTR_ASSERT(top_block_name == bitstream_manager.block_name(block_hierarchy[0]));
|| 0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1]))); block_hierarchy.erase(block_hierarchy.begin());
if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))) {
block_hierarchy.erase(block_hierarchy.begin());
} else if (0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[1]))) {
block_hierarchy.erase(block_hierarchy.begin());
block_hierarchy.erase(block_hierarchy.begin());
}
/* Build the full hierarchy path */ /* Build the full hierarchy path */
std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME); std::string bit_hierarchy_path(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME);
@ -480,8 +463,7 @@ static void print_verilog_preconfig_top_module_deposit_bitstream(
* 2. Mentor Modelsim prefers using '$deposit' syntax to do so * 2. Mentor Modelsim prefers using '$deposit' syntax to do so
*******************************************************************/ *******************************************************************/
static void print_verilog_preconfig_top_module_load_bitstream( static void print_verilog_preconfig_top_module_load_bitstream(
std::fstream &fp, const ModuleManager &module_manager, std::fstream &fp, const std::string& top_block_name, const CircuitLibrary &circuit_lib,
const ModuleId &top_module, const CircuitLibrary &circuit_lib,
const CircuitModelId &mem_model, const BitstreamManager &bitstream_manager, const CircuitModelId &mem_model, const BitstreamManager &bitstream_manager,
const e_embedded_bitstream_hdl_type &embedded_bitstream_hdl_type) { const e_embedded_bitstream_hdl_type &embedded_bitstream_hdl_type) {
/* Skip the datab port if there is only 1 output port in memory model /* Skip the datab port if there is only 1 output port in memory model
@ -504,11 +486,11 @@ static void print_verilog_preconfig_top_module_load_bitstream(
/* Use assign syntax for Icarus simulator */ /* Use assign syntax for Icarus simulator */
if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) { if (EMBEDDED_BITSTREAM_HDL_IVERILOG == embedded_bitstream_hdl_type) {
print_verilog_preconfig_top_module_force_bitstream( print_verilog_preconfig_top_module_force_bitstream(
fp, module_manager, top_module, bitstream_manager, output_datab_bits); fp, top_block_name, bitstream_manager, output_datab_bits);
/* Use deposit syntax for other simulators */ /* Use deposit syntax for other simulators */
} else if (EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type) { } else if (EMBEDDED_BITSTREAM_HDL_MODELSIM == embedded_bitstream_hdl_type) {
print_verilog_preconfig_top_module_deposit_bitstream( print_verilog_preconfig_top_module_deposit_bitstream(
fp, module_manager, top_module, bitstream_manager, output_datab_bits); fp, top_block_name, bitstream_manager, output_datab_bits);
} }
print_verilog_comment( print_verilog_comment(
@ -641,10 +623,17 @@ int print_verilog_preconfig_top_module(
CircuitModelId sram_model = config_protocol.memory_model(); CircuitModelId sram_model = config_protocol.memory_model();
VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model)); VTR_ASSERT(true == circuit_lib.valid_model_id(sram_model));
/* If we do have the core module, and the dut is specified as core module, the hierarchy path when adding should be the instance name of the core module */
std::string inst_name = generate_fpga_top_module_name();
if (options.dut_module() == generate_fpga_core_module_name()) {
ModuleId parent_module = module_manager.find_module(generate_fpga_top_module_name());
inst_name = module_manager.instance_name(parent_module, core_module, 0);
}
/* Assign FPGA internal SRAM/Memory ports to bitstream values, only output /* Assign FPGA internal SRAM/Memory ports to bitstream values, only output
* when needed */ * when needed */
print_verilog_preconfig_top_module_load_bitstream( print_verilog_preconfig_top_module_load_bitstream(
fp, module_manager, top_module, circuit_lib, sram_model, bitstream_manager, fp, inst_name, circuit_lib, sram_model, bitstream_manager,
options.embedded_bitstream_hdl_type()); options.embedded_bitstream_hdl_type());
/* Add signal initialization: /* Add signal initialization: