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Define Circuit doc improvement 

Added some content, better spacing for understanding and made some changes in the options we show
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Baudouin Chauviere 2018-09-25 11:53:53 -06:00
parent 681cca99a4
commit 70d303dfb5
1 changed files with 60 additions and 58 deletions
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docs/source/arch_lang/circuit_modules.rst
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@ -11,7 +11,7 @@ Define spice_models
.. code-block:: xml
<module_spice_models>
<spice_model type="string" name="string" prefix="string" is_default="int" netlist="string">
<spice_model type="string" name="string" prefix="string" is_default="int" [spice|verilog]_netlist="string">
<transistor-level circuit design features>
</spice_model>
</module_spice_models>
@ -49,19 +49,25 @@ Define spice_models
<port type="string" prefix="string" size="int" default_val="int" spice_model_name="string" mode_select="boolean" is_global="boolean" is_set="boolean" is_reset="boolean" is_config_enable="boolean"/>
</spice_model>
design_technology :
* design_technology :
* type: [cmos|rram]. Specify the type of design technology of the spice_model.
.. note:: Currently, the RRAM-based designs are only supported for multiplexers.
* input_buffer and output_buffer: exist: [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined SPICE netlist.
* input_buffer and output_buffer:
* exist: [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined SPICE netlist.
* spice_model_name: Specify the name of spice model which is used to implement input/output buffer, the type of specified spice model should be inv_buf.
* pass_gate_logic: defined the parameters in pass-gates, which are used in building multiplexers and LUTs.
* spice_model_name: Specify the name of spice model which is used to implement input/output buffer, the type of specified spice model should be pass_gate.
* port: define the port list of a spice model.
* type: can be [input|output|sram|clock]. For programmable modules, such as multip-lexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined.
* type: can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined.
* prefix: the name of the port. Each port will be shown as <prefix>[i], 0≤i<size in SPICE netlists.
@ -81,10 +87,6 @@ design_technology :
* is_config_enable: can be either true or false. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to a global configuration-enable voltage stimuli in testbenches.
* pass_gate_logic: defined the parameters in pass-gates, which are used in building multiplexers and LUTs.
* spice_model_name: Specify the name of spice model which is used to implement input/output buffer, the type of specified spice model should be pass_gate.
Inverters and Buffers
=====================
@ -98,7 +100,7 @@ Inverters and Buffers
.. note:: customized SPICE netlists are not currently supported for inverters and buffers.
design_technology:
* design_technology:
* topology: [inverter|buffer]. Specify the type of this component, can be either an inverter or a buffer.
@ -118,7 +120,7 @@ Pass-gate Logic
.. code-block:: xml
<spice_model type="pass_gate" name="string" prefix="string" netlist="string" is_default="1"/>
<design_technology type="cmos" topology="string" size="int" tapered="off"/>
<design_technology type="cmos" topology="string" nmos_size="int" pmos_size="int" tapered="off"/>
<input_buffer exist="string" spice_model_name="string" />
<output_buffer exist="string" spice_model_name="string" />
<port type="input" prefix="string" size="int"/>
@ -127,7 +129,7 @@ Pass-gate Logic
.. note:: customized SPICE netlists are not currently supported for pass-gate logics.
design_technology:
* design_technology:
* topology: [transmission_gate|pass_transistor]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor.
@ -174,7 +176,7 @@ Multiplexers
.. note:: customized SPICE netlists are not currently supported for multiplexers.
design_technology:
* design_technology:
* structure: can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5].
@ -263,7 +265,7 @@ Flip-Flops
Instructions of defining design parameters:
* port: three types of ports (input, output and clock) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
* port: three types of ports (input, output and clock) should be defined. If the user provides a customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
Hard Logics
===========
@ -315,7 +317,7 @@ Instructions of defining design parameters:
* port: two types of ports (input and output) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
.. wire_param:
* wire_param:
* model_type: can be [pie|T], corresponding to the π-type and T-type RC wire models.
* res_val: specify the total resistance of the wire