diff --git a/docs/source/arch_lang/circuit_modules.rst b/docs/source/arch_lang/circuit_modules.rst
index a68dfa16d..e8338f77b 100644
--- a/docs/source/arch_lang/circuit_modules.rst
+++ b/docs/source/arch_lang/circuit_modules.rst
@@ -11,22 +11,22 @@ Define spice_models
 .. code-block:: xml
 
   <module_spice_models>
-    <spice_model type="string" name="string" prefix="string" is_default="int" netlist="string">
+    <spice_model type="string" name="string" prefix="string" is_default="int" [spice|verilog]_netlist="string">
       <transistor-level circuit design features>
     </spice_model>
   </module_spice_models>
 
 * module_spice_models: the father node for all the spice models. All the spice models should be defined under this XML node. 
 
-* spice_model: the child node defining transistor-level modeling parameters. 
+	* spice_model: the child node defining transistor-level modeling parameters. 
 
-* type: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | sff | hard_logic | iopad ]. Specify the type of this spice model. The provided types cover all the modules in FPGAs. For the spice models in the type of mux/wire/chan_wire/lut, FPGA-SPICE can auto-generate SPICE netlists. For the rest, FPGA-SPICE requires a user-defined SPICE netlists.
+		* type: can be [ inv_buf | pass_gate | mux | wire | chan_wire | sram | lut | ff | sff | hard_logic | iopad ]. Specify the type of this spice model. The provided types cover all the modules in FPGAs. For the spice models in the type of mux/wire/chan_wire/lut, FPGA-SPICE can auto-generate SPICE netlists. For the rest, FPGA-SPICE requires a user-defined SPICE netlists.
 
-* name: define the name of this spice model. The name should be unique and will be used in create the sub-circuit of the spice model in SPICE netlists. Note that for a customized SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized SPICE netlist. FPGA-SPICE will check if the given name is conflicted with any reserved words.
+		* name: define the name of this spice model. The name should be unique and will be used in create the sub-circuit of the spice model in SPICE netlists. Note that for a customized SPICE netlist, the name defined here should be the name of the top-level sub-circuit in the customized SPICE netlist. FPGA-SPICE will check if the given name is conflicted with any reserved words.
 
-* prefix: specify the name of the spice_model to shown in the auto-generated SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique. 
+		* prefix: specify the name of the spice_model to shown in the auto-generated SPICE netlists. The prefix can be the same as the name defined above. And again, the prefix should be unique. 
 
-* is_default: can be [1|0], corresponding to [true|false] respectively. Specify this spice model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-SPICE will find the default spice model defined in the same type and link.  For a spice model type, only one spice model can be set as default.
+		* is_default: can be [1|0], corresponding to [true|false] respectively. Specify this spice model is the default one for some modules, such as multiplexers. If a module is not linked to any spice model by users, FPGA-SPICE will find the default spice model defined in the same type and link.  For a spice model type, only one spice model can be set as default.
 
 * spice_netlist: specify the path and file name of a customized SPICE netlist. For some modules such as SRAMs, FFs, inpad and outpads, FPGA-SPICE does not support auto-generation of the transistor-level sub-circuits because their circuit design are highly dependent on the technology nodes. These circuit designs should be specified by users. For the other modules that can be auto-generated by FPGA-SPICE, user can also define a custom netlist. Multiplexers can not be user-defined.
 
@@ -49,41 +49,43 @@ Define spice_models
     <port type="string" prefix="string" size="int" default_val="int" spice_model_name="string" mode_select="boolean" is_global="boolean" is_set="boolean" is_reset="boolean" is_config_enable="boolean"/>
   </spice_model>
 
-design_technology :
+* design_technology :
 
-* type: [cmos|rram]. Specify the type of design technology of the spice_model. 
+	* type: [cmos|rram]. Specify the type of design technology of the spice_model. 
 
 .. note:: Currently, the RRAM-based designs are only supported for multiplexers.
 
-* input_buffer and output_buffer: exist: [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined SPICE netlist.
+* input_buffer and output_buffer: 
+	
+	* exist: [on|off]. Define the existence of the input_buffer or output_buffer. Note that the existence is valid for all the inputs and outputs. Note that if users want only part of the inputs (or outputs) to be buffered, this is not supported here. A solution can be building a user-defined SPICE netlist.
 
-* spice_model_name: Specify the name of spice model which is used to implement input/output buffer, the type of specified spice model should be inv_buf.
-
-* port: define the port list of a spice model. 
-
-* type: can be [input|output|sram|clock]. For programmable modules, such as multip-lexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined.
-
-* prefix: the name of the port. Each port will be shown as <prefix>[i], 0≤i<size in SPICE netlists.
-
-* size: bandwidth of the port. 
-
-* default_val:  default logic value of a port, which is used as initial logic value of this port in testbench generation. Can be either 0 or 1. We assume each pin of this port has the same default value.
-
-* spice_model_name: only valid when the type of port is sram. Specify the name of spice model which is connected to this port.
-
-* mode_select: can be either true or false. Specify if this port controls the mode switching in a configurable logic block. Only valid when the type of this port is sram. (A configurable logic block can operate in different modes, which is controlled by SRAM bits.) 
-
-* is_global: can be either true or false. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
-
-* is_set: can be either true or false. Specify if this port controls a set signal. Only valid when is_global is true. All the set ports are connected to a global set voltage stimuli in testbenches.
-
-* is_reset: can be either true or false. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches.
-
-* is_config_enable: can be either true or false. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to a global configuration-enable voltage stimuli in testbenches.
+	* spice_model_name: Specify the name of spice model which is used to implement input/output buffer, the type of specified spice model should be inv_buf.
 
 * pass_gate_logic: defined the parameters in pass-gates, which are used in building multiplexers and LUTs.
 
-* spice_model_name: Specify the name of spice model which is used to implement input/output buffer, the type of specified spice model should be pass_gate.
+	* spice_model_name: Specify the name of spice model which is used to implement input/output buffer, the type of specified spice model should be pass_gate.
+
+* port: define the port list of a spice model. 
+
+	* type: can be [input|output|sram|clock]. For programmable modules, such as multiplexers and LUTs, SRAM ports should be defined. For registers, such as FFs and memory banks, clock ports should be defined.
+
+	* prefix: the name of the port. Each port will be shown as <prefix>[i], 0≤i<size in SPICE netlists.
+
+	* size: bandwidth of the port. 
+
+	* default_val:  default logic value of a port, which is used as initial logic value of this port in testbench generation. Can be either 0 or 1. We assume each pin of this port has the same default value.
+
+	* spice_model_name: only valid when the type of port is sram. Specify the name of spice model which is connected to this port.
+
+	* mode_select: can be either true or false. Specify if this port controls the mode switching in a configurable logic block. Only valid when the type of this port is sram. (A configurable logic block can operate in different modes, which is controlled by SRAM bits.) 
+
+	* is_global: can be either true or false. Specify if this port is a global port, which will be routed globally. Note that when multiple global ports are defined with the same name, these global ports will be short-wired together.
+
+	* is_set: can be either true or false. Specify if this port controls a set signal. Only valid when is_global is true. All the set ports are connected to a global set voltage stimuli in testbenches.
+
+	* is_reset: can be either true or false. Specify if this port controls a reset signal. Only valid when is_global is true. All the reset ports are connected to a global reset voltage stimuli in testbenches.
+
+	* is_config_enable: can be either true or false. Only valid when is_global is true. Specify if this port controls a configuration-enable signal. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the config_enable ports are connected to a global configuration-enable voltage stimuli in testbenches.
 
 Inverters and Buffers
 =====================
@@ -98,19 +100,19 @@ Inverters and Buffers
 
 .. note:: customized SPICE netlists are not currently supported for inverters and buffers. 
 
-design_technology:
+* design_technology:
 
-* topology: [inverter|buffer]. Specify the type of this component, can be either an inverter or a buffer.
+	* topology: [inverter|buffer]. Specify the type of this component, can be either an inverter or a buffer.
 
-* size: Specify the driving strength of inverter/buffer. For a buffer, the size is the driving strength of the inverter at the second level. We consider a two-level structure for a buffer here. The support for multi-level structure of a buffer will be introduced in the tapered options.
+	* size: Specify the driving strength of inverter/buffer. For a buffer, the size is the driving strength of the inverter at the second level. We consider a two-level structure for a buffer here. The support for multi-level structure of a buffer will be introduced in the tapered options.
 
-* tapered: [on|off]. Define if the buffer is a tapered (multi-level) buffer. 
+	* tapered: [on|off]. Define if the buffer is a tapered (multi-level) buffer. 
 
-* tap_buf_level: Define the number of levels of a tapered buffer. This parameter is valid only when tapered is turned on.
+	* tap_buf_level: Define the number of levels of a tapered buffer. This parameter is valid only when tapered is turned on.
 
-* f_per_stage: Define the ratio of driving strength between the levels of a tapered buffer. This parameter is valid only when tapered is turned on. Default value is 4.
+	* f_per_stage: Define the ratio of driving strength between the levels of a tapered buffer. This parameter is valid only when tapered is turned on. Default value is 4.
 
-* is_default: Specify that this model is a default choice for input and output buffers.
+	* is_default: Specify that this model is a default choice for input and output buffers.
 
 Pass-gate Logic
 ===============
@@ -118,7 +120,7 @@ Pass-gate Logic
 .. code-block:: xml 
 
   <spice_model type="pass_gate" name="string" prefix="string" netlist="string" is_default="1"/>
-    <design_technology type="cmos" topology="string" size="int" tapered="off"/>
+    <design_technology type="cmos" topology="string" nmos_size="int" pmos_size="int" tapered="off"/>
     <input_buffer exist="string" spice_model_name="string" />
     <output_buffer exist="string" spice_model_name="string" />
     <port type="input" prefix="string" size="int"/>
@@ -127,15 +129,15 @@ Pass-gate Logic
 
 .. note:: customized SPICE netlists are not currently supported for pass-gate logics. 
 
-design_technology:
+* design_technology:
 
-* topology: [transmission_gate|pass_transistor]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor.
+	* topology: [transmission_gate|pass_transistor]. The transmission gate consists of a NMOS transistor and a PMOS transistor. The pass transistor consists of a NMOS transistor.
 
-* nmos_size: the size of NMOS transistor in a transmission gate or pass_transistor, expressed in terms of the min_width defined in XML node <transistors>.
+	* nmos_size: the size of NMOS transistor in a transmission gate or pass_transistor, expressed in terms of the min_width defined in XML node <transistors>.
 
-* pmos_size: the size of PMOS transistor in a transmission gate, expressed in terms of the min_width defined in XML node <transistors>.
+	* pmos_size: the size of PMOS transistor in a transmission gate, expressed in terms of the min_width defined in XML node <transistors>.
 
-* is_default: Specify that this model is a default choice for pass-gate logics.
+	* is_default: Specify that this model is a default choice for pass-gate logics.
 
 SRAMs
 =====
@@ -174,17 +176,17 @@ Multiplexers
 
 .. note:: customized SPICE netlists are not currently supported for multiplexers. 
 
-design_technology: 
+* design_technology: 
 
-* structure: can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5].
+	* structure: can be [tree|multi-level|one-level]. The structure options are valid for SRAM-based multiplexers. For RRAM-based multiplexers, currently we only support the circuit design in [5].
 
-* num_level: specify the number of levels when multi-level structure is selected.
+	* num_level: specify the number of levels when multi-level structure is selected.
 
-* ron: valid only when the type of design technology is rram. Specify the on-resistance of the RRAM device used in the RRAM-based multiplexer. 
+	* ron: valid only when the type of design technology is rram. Specify the on-resistance of the RRAM device used in the RRAM-based multiplexer. 
 
-* roff: valid only when the type of design technology is rram. Specify the off-resistance of the RRAM device used in the RRAM-based multiplexer. 
+	* roff: valid only when the type of design technology is rram. Specify the off-resistance of the RRAM device used in the RRAM-based multiplexer. 
 
-* prog_transistor_size: valid only when the type of design technology is rram. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node <transistors>.
+	* prog_transistor_size: valid only when the type of design technology is rram. Specify the size of programming transistors used in the RRAM-based multiplexer, we use only n-type transistor and the size should be expressed in terms of the min_width defined in XML node <transistors>.
 
 * port: for a multiplexer, the three types of ports, input, output and sram should be defined. 
 
@@ -263,7 +265,7 @@ Flip-Flops
 
 Instructions of defining design parameters:
 
-* port: three types of ports (input, output and clock) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
+* port: three types of ports (input, output and clock) should be defined. If the user provides a customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist.
 
 Hard Logics
 ===========
@@ -315,12 +317,12 @@ Instructions of defining design parameters:
 
 * port: two types of ports (input and output) should be defined. If the user provides an customized SPICE netlist, the bandwidth of ports should be defined to the same as the SPICE netlist. 
 
-.. wire_param:
+* wire_param:
 
-* model_type: can be [pie|T], corresponding to the π-type and T-type RC wire models. 
-* res_val: specify the total resistance of the wire
-* cap_val: specify the total capacitance of the wire.
-* level: specify the number of levels of the RC wire model.
+	* model_type: can be [pie|T], corresponding to the π-type and T-type RC wire models. 
+	* res_val: specify the total resistance of the wire
+	* cap_val: specify the total capacitance of the wire.
+	* level: specify the number of levels of the RC wire model.
 
 :numref:`fig_wire` depicts the modeling for a length-2 channel wire.