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Merge pull request #79 from LNIS-Projects/dev 

[Architecture Languange] Patch the default circuit model definition
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Laboratory for Nano Integrated Systems (LNIS) 2020-08-23 16:20:24 -06:00 committed by GitHub
parent 551c2d79c2 4b3142c4ee
commit 70b8bd1a76
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GPG Key ID: 4AEE18F83AFDEB23
14 changed files with 81 additions and 16 deletions
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4
docs/source/manual/arch_lang/circuit_library.rst
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@ -78,9 +78,9 @@ Here, we focus these common syntax and we will detail special syntax in :ref:`ci
.. warning:: ``prefix`` may be deprecated soon
.. note:: Multiplexers cannot be user-defined.
.. warning:: Multiplexers cannot be user-defined.
.. note:: For a circuit model type, only one circuit model can be set as default.
.. warning:: For a circuit model type, only one circuit model is allowed to be set as default. If there is only one circuit model defined in a type, it will be considered as the default automatically.
.. note:: If ``<spice_netlist>`` or ``<verilog_netlist>`` are not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs.

46
libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
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@ -197,6 +197,43 @@ size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib,
return num_err;
}
/************************************************************************
* A generic function to search each default circuit model by types
* that have been defined by users.
* If a type of circuit model is defined, we expect there is a default model
* to be specified
***********************************************************************/
static
size_t check_default_circuit_model_by_types(const CircuitLibrary& circuit_lib) {
size_t num_err = 0;
for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_TYPES; ++itype) {
std::vector<CircuitModelId> curr_models = circuit_lib.models_by_type(e_circuit_model_type(itype));
if (0 == curr_models.size()) {
continue;
}
/* Go through the models and try to find a default one */
size_t found_default_counter = 0;
for (const auto& curr_model : curr_models) {
if (true == circuit_lib.model_is_default(curr_model)) {
found_default_counter++;
}
}
if (0 == found_default_counter) {
VTR_LOG_ERROR("Miss a default circuit model for the type %s! Try to define it in your architecture file!\n",
CIRCUIT_MODEL_TYPE_STRING[itype]);
num_err++;
}
if (1 < found_default_counter) {
VTR_LOG_ERROR("Found >1 default circuit models for the type %s! Expect only one!\n",
CIRCUIT_MODEL_TYPE_STRING[itype]);
num_err++;
}
}
return num_err;
}
/************************************************************************
* A generic function to find the default circuit model with a given type
* If not found, we give an error
@ -207,9 +244,9 @@ size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib,
size_t num_err = 0;
if (CircuitModelId::INVALID() == circuit_lib.default_model(circuit_model_type)) {
VTR_LOG_ERROR("A default circuit model for the type %s! Try to define it in your architecture file!\n",
VTR_LOG_ERROR("Miss a default circuit model for the type %s! Try to define it in your architecture file!\n",
CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]);
exit(1);
num_err++;
}
return num_err;
@ -626,7 +663,10 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_LUT, lut_port_types_required);
/* 10. We must have default circuit models for these types: MUX, channel wires and wires */
/* 10. For each type of circuit models that are define, we must have 1 default model
* We must have default circuit models for these types: MUX, channel wires and wires
*/
num_err += check_default_circuit_model_by_types(circuit_lib);
num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_MUX);
num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_CHAN_WIRE);
num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_WIRE);

18
libopenfpga/libarchopenfpga/src/circuit_library.cpp
View File

@ -2,6 +2,7 @@
#include <algorithm>
#include "vtr_assert.h"
#include "vtr_log.h"
#include "openfpga_port_parser.h"
#include "circuit_library.h"
@ -2108,6 +2109,23 @@ void CircuitLibrary::build_timing_graphs() {
return;
}
/* Automatically identify the default models for each type*/
void CircuitLibrary::auto_detect_default_models() {
/* Go through the model fast look-up */
for (const auto& curr_type_models : model_lookup_) {
if ( (1 == curr_type_models.size())
&& (false == model_is_default(curr_type_models[0]))) {
/* This is the only model in this type,
* it is safe to set it to be default
* Give a warning for users
*/
set_model_is_default(curr_type_models[0], true);
VTR_LOG_WARN("Automatically set circuit model '%s' to be default in its type.\n",
model_name(curr_type_models[0]).c_str());
}
}
}
/************************************************************************
* Internal mutators: build timing graphs
***********************************************************************/

4
libopenfpga/libarchopenfpga/src/circuit_library.h
View File

@ -461,6 +461,10 @@ class CircuitLibrary {
public: /* Public Mutators: builders */
void build_model_links();
void build_timing_graphs();
/* Automatically identify the default models for each type,
* suggest to do this after circuit library is built
*/
void auto_detect_default_models();
public: /* Internal mutators: build timing graphs */
void add_edge(const CircuitModelId& model_id,
const CircuitPortId& from_port, const size_t& from_pin,

3
libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
View File

@ -52,6 +52,9 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
auto xml_circuit_models = get_single_child(xml_openfpga_arch, "circuit_library", loc_data);
openfpga_arch.circuit_lib = read_xml_circuit_library(xml_circuit_models, loc_data);
/* Automatically identify the default models for circuit library */
openfpga_arch.circuit_lib.auto_detect_default_models();
/* Build the internal links for the circuit library */
openfpga_arch.circuit_lib.build_model_links();

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
View File

@ -184,7 +184,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
View File

@ -184,7 +184,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
View File

@ -184,7 +184,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
View File

@ -175,7 +175,7 @@
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<circuit_model type="iopad" name="iopad" prefix="iopad" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
@ -184,7 +184,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
View File

@ -184,7 +184,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
View File

@ -184,7 +184,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
View File

@ -189,7 +189,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

2
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
View File

@ -189,7 +189,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
View File

@ -154,7 +154,7 @@
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
@ -204,7 +204,7 @@
<port type="input" prefix="outpad" size="1"/>
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>